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* InstCombine: simplify comparisons to zero of (shl %x, Cst) or (mul %x, Cst)Arnaud A. de Grandmaison2013-03-252-0/+225
| | | | | | | | This simplification happens at 2 places : - using the nsw attribute when the shl / mul is used by a sign test - when the shl / mul is compared for (in)equality to zero git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177856 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed isNullOrUndef => IsNullOrUndef and isNoopInstruction => ↵Michael Gottesman2013-03-253-14/+14
| | | | | | IsNoopInstruction so that all helper functions are named similarly in ObjCARC.h. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177855 91177308-0d34-0410-b5e6-96231b3b80d8
* Mention the new TableGen pattern format in the release notes.Jakob Stoklund Olesen2013-03-251-0/+6
| | | | | | Make threats about removing the old syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177848 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Fix handling of vector argumentsJustin Holewinski2013-03-243-7/+83
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177847 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up Sparc patterns.Jakob Stoklund Olesen2013-03-241-5/+5
| | | | | | | The types of register variables no longer need to be specified in output patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177845 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow types to be omitted in output patterns.Jakob Stoklund Olesen2013-03-242-0/+16
| | | | | | | | | | This syntax is now preferred: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; There is no reason to repeat the types in the output pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177844 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow TableGen DAG arguments to be just a name.Jakob Stoklund Olesen2013-03-243-16/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | DAG arguments can optionally be named: (dag node, node:$name) With this change, the node is also optional: (dag node, node:$name, $name) The missing node is treated as an UnsetInit, so the above is equivalent to: (dag node, node:$name, ?:$name) This syntax is useful in output patterns where we currently require the types of variables to be repeated: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr i32:$b, i32:$c)>; This is preferable: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177843 91177308-0d34-0410-b5e6-96231b3b80d8
* GettingStarted: Add Git clone instructions for compiler-rt and test-suiteTobias Grosser2013-03-241-1/+18
| | | | | | Contributed-by: Thomas Schwinge <thomas@codesourcery.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177841 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor cleanups. No functionality change.Jakub Staszak2013-03-241-6/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177837 91177308-0d34-0410-b5e6-96231b3b80d8
* Use dyn_cast instead of isa && cast.Jakub Staszak2013-03-241-8/+6
| | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177836 91177308-0d34-0410-b5e6-96231b3b80d8
* Give Sparc instruction patterns direct types instead of register classes.Jakob Stoklund Olesen2013-03-242-88/+75
| | | | | | | Also update the documentation since Sparc is the nicest backend, and used as an example in WritingAnLLVMBackend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177835 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow direct value types to be used in instruction 'set' patterns.Jakob Stoklund Olesen2013-03-241-2/+24
| | | | | | | | | | | | This makes it possible to define instruction patterns like this: def LDri : F3_2<3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr), "ld [$addr], $dst", [(set i32:$dst, (load ADDRri:$addr))]>; ~~~ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177834 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC ZERO register needs a register number of 0.Hal Finkel2013-03-231-0/+1
| | | | | | | | | In order for the new ZERO register to be used with MC, etc. we need to specify its register number (0). Thanks to Kai for reporting the problem! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177833 91177308-0d34-0410-b5e6-96231b3b80d8
* Note in PPCFunctionInfo VRSAVE spillsHal Finkel2013-03-234-14/+34
| | | | | | | | | | | | In preparation for using the new register scavenger capability for providing more than one register simultaneously, specifically note functions that have spilled VRSAVE (currently, this can happen only in functions that use the setjmp intrinsic). As with CR spilling, such functions will need to provide two emergency spill slots to the scavenger. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177832 91177308-0d34-0410-b5e6-96231b3b80d8
* MCize the bcl instruction in PPCAsmPrinterHal Finkel2013-03-231-4/+5
| | | | | | | | | I recently added a BCL instruction definition as part of implementing SjLj support. This can also be used to MCize bcl emission in the asm printer. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177830 91177308-0d34-0410-b5e6-96231b3b80d8
* Use direct types in Sparc def : Pat patterns.Jakob Stoklund Olesen2013-03-231-10/+10
| | | | | | | | | | The SelectionDAG graph has MVT type labels, not register classes, so this makes it clearer what is happening. This notation is also robust against adding more types to the IntRegs register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177829 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow direct value types in pattern definitions.Jakob Stoklund Olesen2013-03-232-5/+29
| | | | | | | | | | | | | | | | | Just like register classes, value types can be used in two ways in patterns: (sext_inreg i32:$src, i16) In a named leaf node like i32:$src, the value type simply provides the type of the node directly. This simplifies type inference a lot compared to the current practice of specifiying types indirectly with register classes. As an unnamed leaf node, like i16 above, the value type represents itself as an MVT::Other immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177828 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup some unused reg. scavenger parameters in PPCRegisterInfoHal Finkel2013-03-232-33/+19
| | | | | | | | | | | These spilling functions will eventually make use of the register scavenger, however, they'll do so by taking advantage of PEI's virtual-register-based delayed scavenging mechanism. As a result, these function parameters will not be used, and can be removed. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177827 91177308-0d34-0410-b5e6-96231b3b80d8
* Make all unnamed RegisterClass TreePatternNodes typed MVT::i32.Jakob Stoklund Olesen2013-03-232-21/+21
| | | | | | | | | | | | | | | | | | | | | A register class can appear as a leaf TreePatternNode with and without a name: (COPY_TO_REGCLASS GPR:$src, F8RC) In a named leaf node like GPR:$src, the register class provides type information for the named variable represented by the node. The TypeSet for such a node is the set of value types that the register class can represent. In an unnamed leaf node like F8RC above, the register class represents itself as a kind of immediate. Such a node has the type MVT::i32, we'll never create a virtual register representing it. This change makes it possible to remove the special handling of COPY_TO_REGCLASS in CodeGenDAGPatterns.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177825 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead PPC LR spilling codeHal Finkel2013-03-231-30/+8
| | | | | | | | | | The LR register is unconditionally reserved, and its spilling and restoration is handled by the prologue/epilogue code. As a result, it is never explicitly spilled by the register allocator. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177823 91177308-0d34-0410-b5e6-96231b3b80d8
* Plug a memory leak in FileCheck when the input file is empty.Benjamin Kramer2013-03-231-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177822 91177308-0d34-0410-b5e6-96231b3b80d8
* Move X86-dependent test into the right subdirectory.Benjamin Kramer2013-03-231-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177821 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the type legality check from the SelectionDAGBuilder when it lowers ↵Owen Anderson2013-03-232-1/+20
| | | | | | | | | | | | @llvm.fmuladd to ISD::FMA nodes. Performing this check unilaterally prevented us from generating FMAs when the incoming IR contained illegal vector types which would eventually be legalized to underlying types that *did* support FMA. For example, an @llvm.fmuladd on an OpenCL float16 should become a sequence of float4 FMAs, not float4 fmul+fadd's. NOTE: Because we still call the target-specific profitability hook, individual targets can reinstate the old behavior, if desired, by simply performing the legality check inside their callback hook. They can also perform more sophisticated legality checks, if, for example, some illegal vector types can be productively implemented as FMAs, but not others. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177820 91177308-0d34-0410-b5e6-96231b3b80d8
* Change method name ClearRefCount => ClearKnownPositiveRefCount to match the ↵Michael Gottesman2013-03-231-4/+4
| | | | | | name of the member that it is modifying. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177818 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed the method name PtrState.IsKnownIncremented() to ↵Michael Gottesman2013-03-231-3/+3
| | | | | | | | | PtrState.HasKnownPositiveRefCount(). Now said method matches namewise every other method which refers to the member KnownPositiveRefCount of the class PtrState. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177816 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comparison of mixed signednessHal Finkel2013-03-231-1/+1
| | | | | | | | | | | 177774 broke the lld-x86_64-darwin11 builder; error: error: comparison of integers of different signs: 'int' and 'size_type' (aka 'unsigned long') for (SI = 0; SI < Scavenged.size(); ++SI) ~~ ^ ~~~~~~~~~~~~~~~~ Fix this by making SI also unsigned. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177780 91177308-0d34-0410-b5e6-96231b3b80d8
* [docs] Slight reword for precision.Sean Silva2013-03-221-1/+1
| | | | | | | | The new wording cannot be construed as suggesting the use of SmallVectorImpl<T> as e.g. a class member (just because the class happens to be in an interface). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177778 91177308-0d34-0410-b5e6-96231b3b80d8
* [docs] Document usage of SmallVectorImpl in interfaces.Sean Silva2013-03-221-0/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177775 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow the register scavenger to spill multiple registersHal Finkel2013-03-2210-43/+84
| | | | | | | | | | | | | | | | | | This patch lets the register scavenger make use of multiple spill slots in order to guarantee that it will be able to provide multiple registers simultaneously. To support this, the RS's API has changed slightly: setScavengingFrameIndex / getScavengingFrameIndex have been replaced by addScavengingFrameIndex / isScavengingFrameIndex / getScavengingFrameIndices. In forthcoming commits, the PowerPC backend will use this capability in order to implement the spilling of condition registers, and some special-purpose registers, without relying on r0 being reserved. In some cases, spilling these registers requires two GPRs: one for addressing and one to hold the value being transferred. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774 91177308-0d34-0410-b5e6-96231b3b80d8
* Support in AAEvaluator to print alias queries of loads/stores with TBAA tags.Manman Ren2013-03-222-0/+176
| | | | | | | | | | Add "evaluate-tbaa" to print alias queries of loads/stores. Alias queries between pointers do not include TBAA tags. Add testing case for "placement new". TBAA currently says NoAlias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177772 91177308-0d34-0410-b5e6-96231b3b80d8
* Kill every call to @clang.arc.use in the ARC contract phase.John McCall2013-03-226-3/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177769 91177308-0d34-0410-b5e6-96231b3b80d8
* Update test. There may be multiple catches, but those will be cleaned up.Bill Wendling2013-03-221-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177758 91177308-0d34-0410-b5e6-96231b3b80d8
* Add all clauses when merging the landing pads. Duplicates will be handled ↵Bill Wendling2013-03-221-24/+14
| | | | | | later on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177757 91177308-0d34-0410-b5e6-96231b3b80d8
* Swap the DIFile in DILexicalBlockFile out for the raw name/directory pairDavid Blaikie2013-03-223-11/+1
| | | | | | This is the last change in transitioning all DIScopes to have a common prefix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177756 91177308-0d34-0410-b5e6-96231b3b80d8
* reorder the fields in DILexicalBlockFile to match the common prefix for DIScopesDavid Blaikie2013-03-223-23/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177754 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverted r176374. In some cases the lit.site.cfg file does not get generated ↵Galina Kistanova2013-03-221-0/+5
| | | | | | in tools/clang/tools/extra. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177751 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use the removed API.Bill Wendling2013-03-221-5/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177749 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r177675. This is language-specific and shouldn't be in the API.Bill Wendling2013-03-222-10/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177748 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and ↵Jyotsna Verma2013-03-229-494/+1948
| | | | | | word. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177747 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor out the DIFile parameter to DILexicalBlock to refer to the raw ↵David Blaikie2013-03-229-19/+9
| | | | | | file/directory pair git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177742 91177308-0d34-0410-b5e6-96231b3b80d8
* fix small doc typoEli Bendersky2013-03-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177737 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730Michel Danzer2013-03-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177736 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove ABI-duplicated call instruction patterns.Ulrich Weigand2013-03-228-148/+71
| | | | | | | | | | | | | | | | | | | | We currently have a duplicated set of call instruction patterns depending on the ABI to be followed (Darwin vs. Linux). This is a bit odd; while the different ABIs will result in different instruction sequences, the actual instructions themselves ought to be independent of the ABI. And in fact it turns out that the only nontrivial difference between the two sets of patterns is that in the PPC64 Linux ABI, the instruction used for indirect calls is marked to take X11 as extra input register (which is indeed used only with that ABI to hold an incoming environment pointer for nested functions). However, this does not need to be hard-coded at the .td pattern level; instead, the C++ code expanding calls can simply add that use, just like it adds uses for argument registers anyway. No change in generated code expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177735 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename memrr ptrreg and offreg components.Ulrich Weigand2013-03-222-22/+22
| | | | | | | | | | | | | Currently, the sub-operand of a memrr address that corresponds to what hardware considers the base register is called "offreg", while the sub-operand that corresponds to the offset is called "ptrreg". To avoid confusion, this patch simply swaps the named of those two sub-operands and updates all uses. No functional change is intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177734 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix swapped BasePtr and Offset in pre-inc memory addresses.Ulrich Weigand2013-03-224-20/+40
| | | | | | | | | | | | | | | | | | | | | | PPCTargetLowering::getPreIndexedAddressParts currently provides the base part of a memory address in the offset result, and the offset part in the base result. That swap is then undone again when an MI instruction is generated (in PPCDAGToDAGISel::Select for loads, and using .md Pat patterns for stores). This patch reverts this double swap, to make common code and back-end be in sync as to which part of the address is base and which is offset. To avoid performance regressions in certain cases, target code now checks whether the choice of base register would be rejected for pre-inc accesses by common code, and attempts to swap base and offset again in such cases. (Overall, this means that now pre-ice accesses are generated *more* frequently than before.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177733 91177308-0d34-0410-b5e6-96231b3b80d8
* Tighten iaddroff ComplexPattern.Ulrich Weigand2013-03-221-4/+4
| | | | | | | | | | | | | | | | | | | The iaddroff ComplexPattern is supposed to recognize displacement expressions that have been processed by a SelectAddressRegImm, which means it needs to accept TargetConstant and TargetGlobalAddress nodes. Currently, it erroneously also accepts some other nodes, in particular Constant and PPCISD::Lo. While this problem is currently latent, it would cause wrong-code bugs with a follow-on patch I'm about to commit, so this patch tightens the ComplexPattern. The equivalent change is made in PPCDAGToDAGISel::Select, where pre-inc load patterns are handled (as opposed to store patterns, the loads are handled in C++ code without making use of the .td ComplexPattern). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177732 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the xaddroff ComplexPattern.Ulrich Weigand2013-03-223-31/+18
| | | | | | | | | | | The xaddroff pattern is currently (mistakenly) used to recognize the *base* register in pre-inc store patterns. This patch replaces those uses by ptr_rc_nor0 (as is elsewhere done to match the base register of an address), and removes the now unused ComplexPattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177731 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsicsMichel Danzer2013-03-224-15/+5
| | | | | | | | | | | | | | | | | Fixes wrong lighting in some corner cases with r600g and radeonsi, e.g. manifested by failure of two piglit/glean tests and intermittent black patches in many apps. Tested on SI and RS880. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62012 [radeonsi] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58150 [r600g] NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177730 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] Change the way we report the alloca frame on stack-buff-overflow.Kostya Serebryany2013-03-221-8/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: the function name was stored by the compiler as a constant string and the run-time was printing it. Now: the PC is stored instead and the run-time prints the full symbolized frame. This adds a couple of instructions into every function with non-empty stack frame, but also reduces the binary size because we store less strings (I saw 2% size reduction). This change bumps the asan ABI version to v3. llvm part. Example of report (now): ==31711==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7fffa77cf1c5 at pc 0x41feb0 bp 0x7fffa77cefb0 sp 0x7fffa77cefa8 READ of size 1 at 0x7fffa77cf1c5 thread T0 #0 0x41feaf in Frame0(int, char*, char*, char*) stack-oob-frames.cc:20 #1 0x41f7ff in Frame1(int, char*, char*) stack-oob-frames.cc:24 #2 0x41f477 in Frame2(int, char*) stack-oob-frames.cc:28 #3 0x41f194 in Frame3(int) stack-oob-frames.cc:32 #4 0x41eee0 in main stack-oob-frames.cc:38 #5 0x7f0c5566f76c (/lib/x86_64-linux-gnu/libc.so.6+0x2176c) #6 0x41eb1c (/usr/local/google/kcc/llvm_cmake/a.out+0x41eb1c) Address 0x7fffa77cf1c5 is located in stack of thread T0 at offset 293 in frame #0 0x41f87f in Frame0(int, char*, char*, char*) stack-oob-frames.cc:12 <<<<<<<<<<<<<< this is new This frame has 6 object(s): [32, 36) 'frame.addr' [96, 104) 'a.addr' [160, 168) 'b.addr' [224, 232) 'c.addr' [288, 292) 's' [352, 360) 'd' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177724 91177308-0d34-0410-b5e6-96231b3b80d8
* tsan: fix the testDmitry Vyukov2013-03-221-1/+1
| | | | | | | | Add missed file from r177717 commit that adds __tsan_vptr_read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177719 91177308-0d34-0410-b5e6-96231b3b80d8
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