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* Clean up tailing whitespacesMichael Liao2012-10-031-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165182 91177308-0d34-0410-b5e6-96231b3b80d8
* Added instregex support to TableGen subtarget emitter.Andrew Trick2012-10-034-12/+95
| | | | | | | | This allows the processor-specific machine model to override selected base opcodes without any fanciness. e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165180 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget emitter, nearly first class support for SchedAlias.Andrew Trick2012-10-033-130/+229
| | | | | | | | | A processor can now arbitrarily alias one SchedWrite onto another. Only the SchedAlias definition need be within the processor model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or transitively refer to another alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165179 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup TableGen subtarget emitter.Andrew Trick2012-10-032-6/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165178 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Default to the 'm' constraint. This matches the behavior of theChad Rosier2012-10-031-3/+3
| | | | | | | MSVC compiler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165174 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add support in the X86AsmPrinter for printing memory referencesChad Rosier2012-10-033-0/+70
| | | | | | | | | | | | in the Intel syntax. The MC layer supports emitting in the Intel syntax, but this would require the inline assembly MachineInstr to be lowered to an MCInst before emission. This is potential future work, but for now emitting directly from the MachineInstr suffices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165173 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch moves from using a hard coded number (4) Jack Carter2012-10-031-2/+4
| | | | | | | | | | | | | | | for the number of bytes in a particular instruction to using const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode()); Desc.getSize() This is necessary with the advent of 16 bit instructions with mips16 and micromips. It is also puts Mips in compliance with the other targets for getting instruction size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165171 91177308-0d34-0410-b5e6-96231b3b80d8
* tblgen: Remove last traces of old TableGenMain API.Sean Silva2012-10-035-76/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165168 91177308-0d34-0410-b5e6-96231b3b80d8
* tblgen: Migrate llvm-tblgen to new TableGenMain API.Sean Silva2012-10-031-82/+77
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165166 91177308-0d34-0410-b5e6-96231b3b80d8
* tblgen: Put new TableGenMain API in place.Sean Silva2012-10-032-0/+27
| | | | | | | | In order to avoid rev-lock with Clang when moving to the new API, also preserve the current API temporarily and insert a shim to implement the new API in terms of the old. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165165 91177308-0d34-0410-b5e6-96231b3b80d8
* Add function to return return attributes.Bill Wendling2012-10-031-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165164 91177308-0d34-0410-b5e6-96231b3b80d8
* Update to use the predicate methods to query if an attribute exists.Bill Wendling2012-10-031-17/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165163 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a cycle in the DAG. In this code we replace multiple loads with a single ↵Nadav Rotem2012-10-032-7/+50
| | | | | | | | | | | | | load and multiple stores with a single load. We create the wide loads and stores (and their chains) before we remove the scalar loads and stores and fix the DAG chain. We attempted to merge loads with a different chain. When that happened, the assumption that it is safe to RAUW broke and a cycle was introduced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165148 91177308-0d34-0410-b5e6-96231b3b80d8
* Use unsigned long long instead of uin64_t for OS where that matters.Nick Kledzik2012-10-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165147 91177308-0d34-0410-b5e6-96231b3b80d8
* Typos.Chad Rosier2012-10-032-5/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165141 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't call getAsUnsignedInteger directly, it fails to compile if uint64_t is ↵Benjamin Kramer2012-10-031-1/+5
| | | | | | | | not "unsigned long long". while there add more test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165140 91177308-0d34-0410-b5e6-96231b3b80d8
* Add getAsUnsignedInteger test case that checks that known bad values are ↵Nick Kledzik2012-10-031-0/+19
| | | | | | rejected git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165136 91177308-0d34-0410-b5e6-96231b3b80d8
* No need to call functions which do the same thing as the default.Bill Wendling2012-10-031-4/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165135 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove assert that's too restrictive.Bill Wendling2012-10-031-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165134 91177308-0d34-0410-b5e6-96231b3b80d8
* Add methods which query for the specific attribute instead of using theBill Wendling2012-10-035-16/+148
| | | | | | | enums. This allows for better encapsulation of the Attributes class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165132 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement .rel relocation for R_ARM_ABS32 in MCJIT.Tim Northover2012-10-032-2/+26
| | | | | | Patch by Amara Emerson. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165128 91177308-0d34-0410-b5e6-96231b3b80d8
* This Patch corrects a problem whereby the optimization to use a faster dividePreston Gurd2012-10-031-5/+15
| | | | | | | | | | | | | | | | instruction (for Intel Atom) was not being done by Clang, because the type context used by Clang is not the default context. It fixes the problem by getting the global context types for each div/rem instruction in order to compare them against the types in the BypassTypeMap. Tests for this will be done as a separate patch to Clang. Patch by Tyler Nowicki. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165126 91177308-0d34-0410-b5e6-96231b3b80d8
* A DAGCombine optimization for mergeing consecutive stores to memory. The ↵Nadav Rotem2012-10-032-0/+668
| | | | | | | | | | | | | | | | | | | | | | | optimization is not profitable in many cases because modern processors perform multiple stores in parallel and merging stores prior to merging requires extra work. We handle two main cases: 1. Store of multiple consecutive constants: q->a = 3; q->4 = 5; In this case we store a single legal wide integer. 2. Store of multiple consecutive loads: int a = p->a; int b = p->b; q->a = a; q->b = b; In this case we load/store either ilegal vector registers or legal wide integer registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165125 91177308-0d34-0410-b5e6-96231b3b80d8
* Set up MCSchedModel after detecting the CPU type in X86SubTarget.Preston Gurd2012-10-031-0/+4
| | | | | | | | | | | Corrects a problem whereby MCSchedModel was not being set up when the CPU type was auto-detected. Patch by Andy Zhang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165122 91177308-0d34-0410-b5e6-96231b3b80d8
* tsan: update the test for new atomic enumsDmitry Vyukov2012-10-031-80/+80
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165109 91177308-0d34-0410-b5e6-96231b3b80d8
* tsan: update the test for new atomic enumsDmitry Vyukov2012-10-031-40/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165108 91177308-0d34-0410-b5e6-96231b3b80d8
* tsan: prepare for migration to new memory_order enum values (ABI compatible)Dmitry Vyukov2012-10-031-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165107 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug in the ExecutionDependencyFix pass that caused dependencies to ↵Silviu Baranga2012-10-032-3/+28
| | | | | | not propagate through implicit defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165102 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an issue where we failed to adjust the alignment constraint onChandler Carruth2012-10-032-0/+37
| | | | | | | | a memcpy to reflect that '0' has a different meaning when applied to a load or store. Now we correctly use underaligned loads and stores for the test case added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165101 91177308-0d34-0410-b5e6-96231b3b80d8
* Try to use a better set of abstractions for computing the alignmentChandler Carruth2012-10-032-20/+87
| | | | | | | | | | | | | | | | | | | | necessary during rewriting. As part of this, fix a real think-o here where we might have left off an alignment specification when the address is in fact underaligned. I haven't come up with any way to trigger this, as there is always some other factor that reduces the alignment, but it certainly might have been an observable bug in some way I can't think of. This also slightly changes the strategy for placing explicit alignments on loads and stores to only do so when the alignment does not match that required by the ABI. This causes a few redundant alignments to go away from test cases. I've also added a couple of tests that really push on the alignment that we end up with on loads and stores. More to come here as I try to fix an underlying bug I have conjectured and produced test cases for, although it's not clear if this bug is the one currently hitting dragonegg's gcc47 bootstrap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165100 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 165051-165049 while looking into the foreach.m failure inEric Christopher2012-10-035-95/+27
| | | | | | | more detail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165099 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix doxygen comment to match function name.Craig Topper2012-10-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165094 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused function that used to get itineraries from SubTargetFeatures. ↵Craig Topper2012-10-032-28/+0
| | | | | | This is done from MCSubTargetInfo these days. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165092 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix 80-column violationCraig Topper2012-10-031-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165089 91177308-0d34-0410-b5e6-96231b3b80d8
* test/ExecutionEngine/MCJIT: MCJIT should work also on mingw.NAKAMURA Takumi2012-10-032-2/+2
| | | | | | FIXME: Also cygwin? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165081 91177308-0d34-0410-b5e6-96231b3b80d8
* Third try at fixing this. ;] Go back to using std::remove_if, which hasChandler Carruth2012-10-031-8/+28
| | | | | | | | | | most of the behavior we want, but wrap the predicate in one which erases elements from the set if they pass the predicate. Oh what I wouldn't give for a lambda here. Let me know if the predicate wrapping is too much magic. ;] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165076 91177308-0d34-0410-b5e6-96231b3b80d8
* The early if conversion pass is ready to be used as an opt-in.Jakob Stoklund Olesen2012-10-033-5/+11
| | | | | | | | | | | Enable the pass by default for targets that request it, and change the -enable-early-ifcvt to the opposite -disable-early-ifcvt. There are still some x86 regressions when enabling early if-conversion because of the missing machine models. Disable the pass for x86 until machine models are added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165075 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch the SetVector::remove_if implementation to use partition whichChandler Carruth2012-10-032-3/+6
| | | | | | | | | | | | | | preserves the values of the relocated entries, unlikely remove_if. This allows walking them and erasing them. Also flesh out the predicate we are using for this to support the various constraints actually imposed on a UnaryPredicate -- without this we can't compose it with std::not1. Thanks to Sean Silva for the review here and noticing the issue with std::remove_if. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165073 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a serious X86 instruction selection bug. InEvan Cheng2012-10-022-3/+30
| | | | | | | | | | | | | | X86DAGToDAGISel::PreprocessISelDAG(), isel is moving load inside callseq_start / callseq_end so it can be folded into a call. This can create a cycle in the DAG when the call is glued to a copytoreg. We have been lucky this hasn't caused too many issues because the pre-ra scheduler has special handling of call sequences. However, it has caused a crash in a specific tailcall case. rdar://12393897 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165072 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Don't use a debug location for frame setup instructions in the"Eric Christopher2012-10-023-39/+5
| | | | | | | This reverts 165055 and 165052 temporarily while I look at debugger failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165071 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 165057, per Jim's request. This requires further discussion.Chad Rosier2012-10-022-33/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165069 91177308-0d34-0410-b5e6-96231b3b80d8
* The mips 64bit instructions DSLL, DSRA, DSRL, DEXT and DINS get transformed ↵Jack Carter2012-10-026-56/+54
| | | | | | | | | | | | | by the assembler or through codegen direct object output to other variants based on the value of the immediate values of the operands. If the code is generated as assembler, this transformation does not occur assuming that it will occur later in the assembler. This code was originally called from MipsAsmPrinter.cpp and we needed to check for OutStreamer.hasRawTextSupport(). This was not a good place for it and has been moved to MCTargetDesc/MipsMCCodeEmitter.cpp where both direct object and the assembler use it it automagically. The test cases have been checked in for a number of weeks now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165067 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the new SROA to handle cases where an alloca that has already beenChandler Carruth2012-10-023-0/+59
| | | | | | | | | | | | | | | | scheduled for processing on the worklist eventually gets deleted while we are processing another alloca, fixing the original test case in PR13990. To facilitate this, add a remove_if helper to the SetVector abstraction. It's not easy to use the standard abstractions for this because of the specifics of SetVectors types and implementation. Finally, a nice small test case is included. Thanks to Benjamin for the fantastic reduced test case here! All I had to do was delete some empty basic blocks! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165065 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up these doxygen comments to follow the proposed new style. ThisChandler Carruth2012-10-021-21/+22
| | | | | | | also makes it more consistent with Clang and several passes' doxygen style. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165064 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure to put our sret argument into %rax on x86-64. Fixes PR13563!Nick Lewycky2012-10-022-2/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165063 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the old coalescer algorithm.Jakob Stoklund Olesen2012-10-021-344/+1
| | | | | | | The new algorithm has been enabled by default for almost a week now and seems to be stable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165062 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle reserved registers more accurately in handleMove().Jakob Stoklund Olesen2012-10-021-8/+7
| | | | | | | | | | | | Reserved register live ranges look like a set of dead defs - any uses of reserved registers are ignored. Instead of skipping the updating of reserved register operands entirely, just ignore the use operands and treat the def operands normally. No test case, handleMove() is not commonly used yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165060 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add basic support for wildcard MCParsedAsmOperands. This typeChad Rosier2012-10-022-8/+33
| | | | | | | | | | | | | | of operand is specific to MS-style inline assembly and should not be generated when parsing normal assembly. The purpose of the wildcard operands are to allow the AsmParser to match multiple instructions (i.e., MCInsts) to a given ms-style asm statement. For the time being the matcher just returns the first match. This patch only implements wildcard matches for memory operands. Support for register wildcards will be added in the near future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165057 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure the whole live range is covered when values are pruned twice.Jakob Stoklund Olesen2012-10-022-2/+31
| | | | | | | | | | | | | | | | | | | | | | | | JoinVals::pruneValues() calls LIS->pruneValue() to avoid conflicts when overlapping two different values. This produces a set of live range end points that are used to reconstruct the live range (with SSA update) after joining the two registers. When a value is pruned twice, the set of end points was insufficient: v1 = DEF v1 = REPLACE1 v1 = REPLACE2 KILL v1 The end point at KILL would only reconstruct the live range from REPLACE2 to KILL, leaving the range REPLACE1-REPLACE2 dead. Add REPLACE2 as an end point in this case so the full live range is reconstructed. This fixes PR13999. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165056 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow alternate instructions to silence bot.Eric Christopher2012-10-021-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165055 91177308-0d34-0410-b5e6-96231b3b80d8
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