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* NVPTX: Don't even create a regalloc if we're not going to use it.Benjamin Kramer2013-05-311-2/+7
| | | | | | Fixes a leak found by valgrind. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183031 91177308-0d34-0410-b5e6-96231b3b80d8
* [APFloat] Added a unittest for APFloat::getZero.Michael Gottesman2013-05-311-0/+37
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183028 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify how the formulae are rated in Loop Strength Reduce.Quentin Colombet2013-05-314-15/+109
| | | | | | | | | | | | | | | Namely, check if the target allows to fold more that one register in the addressing mode and if yes, adjust the cost accordingly. Prior to this commit, reg1 + scale * reg2 accesses were artificially preferred to reg1 + reg2 accesses. Indeed, the cost model wrongly assumed that reg1 + reg2 needs a temporary register for the computation, whereas it was correctly estimated for reg1 + scale * reg2. <rdar://problem/13973908> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183021 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a way to define the bit range covered by a SubRegIndex.Ahmed Bougacha2013-05-319-36/+113
| | | | | | | | | | | | | | | NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change the instances of SubRegIndex that have a comps template arg to use the ComposedSubRegIndex class instead. In TableGen land, this adds Size and Offset attributes to SubRegIndex, and the ComposedSubRegIndex class, for which the Size and Offset are computed by TableGen. This also adds an accessor in MCRegisterInfo, and Size/Offsets for the X86 and ARM subreg indices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183020 91177308-0d34-0410-b5e6-96231b3b80d8
* Unit test for SCEV fix r182989, PR16130.Andrew Trick2013-05-311-3/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183017 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove useless code from transitioning to new EH schemeKai Nacke2013-05-311-4/+1
| | | | | | | Removes all uses of the variable UsesNewEH. Simply return false in case that no resume instructions were found. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183016 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: permit upper-case BE/LE on setend instructionTim Northover2013-05-312-1/+5
| | | | | | Patch by Amaury de la Vieuville. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183012 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: add fstmx and fldmx instructions for assemblyTim Northover2013-05-316-8/+106
| | | | | | | | | These instructions are deprecated oddities, but we still need to be able to disassemble (and reassemble) them if and when they're encountered. Patch by Amaury de la Vieuville. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183011 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify multiplications by vectors whose elements are powers of 2.Rafael Espindola2013-05-312-16/+456
| | | | | | Patch by Andrea Di Biagio. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183005 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix VEXT encoding corner caseTim Northover2013-05-312-5/+11
| | | | | | | | | | The disassembly of VEXT instructions was too lax in the bits checked. This fixes the case where the instruction affects Q-registers but a misaligned lane was specified (should be UNDEFINED). Patch by Amaury de la Vieuville git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183003 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Don't use LOAD and STORE REVERSED for volatile accessesRichard Sandiford2013-05-316-33/+99
| | | | | | | | | | | | | | | | | | | Unlike most -- hopefully "all other", but I'm still checking -- memory instructions we support, LOAD REVERSED and STORE REVERSED may access the memory location several times. This means that they are not suitable for volatile loads and stores. This patch is a prerequisite for better atomic load and store support. The same principle applies there: almost all memory instructions we support are inherently atomic ("block concurrent"), but LOAD REVERSED and STORE REVERSED are exceptions. Other instructions continue to allow volatile operands. I will add positive "allows volatile" tests at the same time as the "allows atomic load or store" tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183002 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Re-enable support for virtual registers in the final outputJustin Holewinski2013-05-3110-101/+342
| | | | | | | | | | | | Now that 3.3 is branched, we are re-enabling virtual registers to help iron out bugs before the next release. Some of the post-RA passes do not play well with virtual registers, so we disable them for now. The needed functionality of the PrologEpilogInserter pass is copied to a new backend-specific NVPTXPrologEpilog pass. The test for this commit is not breaking the existing tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182998 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Handle mixed track-origins and keep-going settings (llvm part).Evgeniy Stepanov2013-05-312-6/+9
| | | | | | | | | | | | | | | Before this change, each module defined a weak_odr global __msan_track_origins with a value of 1 if origin tracking is enabled, 0 if disabled. If there are modules with different values, any of them may win. If 0 wins, and there is at least one module with 1, the program will most likely crash. With this change, __msan_track_origins is only emitted if origin tracking is on. Then runtime library detects if there is at least one module with origin tracking, and enables runtime support for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182997 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-05-315-42/+55
| | | | | | | | | | The MOV64ri64i32 instruction required hacky MCInst lowering because it was allocated as setting a GR64, but the eventual instruction ("movl") only set a GR32. This converts it into a so-called "MOV32ri64" which still accepts a (appropriate) 64-bit immediate but defines a GR32. This is then converted to the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182991 91177308-0d34-0410-b5e6-96231b3b80d8
* Add links to the System z architecture manual and ABIRichard Sandiford2013-05-311-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182990 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ScalarEvolution::ComputeExitLimitFromCond for 'or' conditions.Andrew Trick2013-05-312-36/+60
| | | | | | | | | | | | | | | | Fixes PR16130 - clang produces incorrect code with loop/expression at -O2. This is a 2+ year old bug that's now holding up the release. It's a case where we knowingly made aggressive assumptions about undefined behavior. These assumptions are wrong when SCEV is computing a subexpression that does not directly control the branch. With this fix, we avoid making assumptions in those cases but still optimize the common case. SCEV's trip count computation for exits controlled by 'or' expressions is now analagous to the trip count computation for loops with multiple exits. I had already fixed the multiple exit case to be conservative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182989 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Big-endian code generation for atomic instructions.Akira Hatanaka2013-05-312-162/+351
| | | | | | | Patch by Jyun-Yan You. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182984 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix wrong comment. Null is not acceptable.Matt Arsenault2013-05-311-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182979 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply with r182909 with a fix to the calculation of the new indices forNick Lewycky2013-05-313-2/+278
| | | | | | | insertelement instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182976 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove debug print added in r182949.Ahmed Bougacha2013-05-301-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182973 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r182937 and r182877.Rafael Espindola2013-05-3026-100/+16
| | | | | | | | | r182877 broke MCJIT tests on ARM and r182937 was working around another failure by r182877. This should make the ARM bots green. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182960 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused member.Rafael Espindola2013-05-301-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182958 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a couple of typos and 80-col.Eric Christopher2013-05-301-19/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182954 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the const_cast only where necessary.Bill Wendling2013-05-301-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182950 91177308-0d34-0410-b5e6-96231b3b80d8
* MCObjectSymbolizer: Switch from IntervalMap to sorted vector, following r182625.Ahmed Bougacha2013-05-302-17/+54
| | | | | | | | This removes the need for the missing SectionRef operator< workaround, and fixes an IntervalMap assert about alignment on MSVC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182949 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement IEEE-754R 2008 nextUp/nextDown functions in the guise of the ↵Michael Gottesman2013-05-303-22/+679
| | | | | | | | function APFloat::next(bool nextDown). rdar://13852078 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182945 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix warning and resulting formatting issue.Paul Redmond2013-05-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182939 91177308-0d34-0410-b5e6-96231b3b80d8
* Revise llvm.vectorizer.width documentationPaul Redmond2013-05-301-2/+4
| | | | | | | | - clarify that vectorizer.width only applies if the vectorizer decides to vectorize. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182938 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use fast isel on this test.Rafael Espindola2013-05-301-1/+1
| | | | | | | | This fixes the test on ARM. Looks like it was broken by r182877. Not sure if this is a bug on fast isel on ARM, but this should help fix the ARM bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182937 91177308-0d34-0410-b5e6-96231b3b80d8
* Force a triple so we don't get bitten by windows' different regalloc.Benjamin Kramer2013-05-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182935 91177308-0d34-0410-b5e6-96231b3b80d8
* Force fragile test to the atom scheduler model.Benjamin Kramer2013-05-301-2/+4
| | | | | | | The pattern the test originally checked for doesn't occur on other -mcpu settings. On atom it's still there though slightly differently scheduled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182933 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a sub-project status update section to the release notes with detailsAshok Thirumurthi2013-05-301-0/+38
| | | | | | | | | on the LLDB 3.3 release. Reviewed by: Greg Clayton and Bill Wendling git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182931 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: allow registers 8-15 in testTim Northover2013-05-301-3/+3
| | | | | | | This test was failing on some hosts when an unexpected register was used for a variable. This just extends the regexp to allow the new x86-64 registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182929 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: use sub-register sequences for MOV*r0 operationsTim Northover2013-05-3018-124/+125
| | | | | | | | | | | | Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182928 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix incorrect parameter name in LIT docs.Sergey Matveev2013-05-301-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182926 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix rematerialization into physical registers.Tim Northover2013-05-301-2/+3
| | | | | | | | | | | | | | | | | r182872 introduced a bug in how the register-coalescer's rematerialization handled defining a physical register. It relied on the output of the coalescer's setRegisters method to determine whether the replacement instruction needed an implicit-def. However, this value isn't necessarily the same as the CopyMI's actual destination register which is what the rest of the basic-block expects us to be defining. The commit changes the rematerializer to use the actual register attached to CopyMI in its decision. This will be tested soon by an X86 patch which moves everything to using MOV32r0 instead of other sizes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182925 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Fix case where a sext load of an i1 type may produce anJustin Holewinski2013-05-302-2/+18
| | | | | | ld.u1 instead of an ld.u8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182924 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: change zext moves to use sub-register infrastructure.Tim Northover2013-05-305-71/+74
| | | | | | | | | | | | 32-bit writes on amd64 zero out the high bits of the corresponding 64-bit register. LLVM makes use of this for zero-extension, but until now relied on custom MCLowering and other code to fixup instructions. Now we have proper handling of sub-registers, this can be done by creating SUBREG_TO_REG instructions at selection-time. Should be no change in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182921 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Enable unaligned accessesRichard Sandiford2013-05-3014-5/+397
| | | | | | | | The code to distinguish between unaligned and aligned addresses was already there, so this is mostly just a switch-on-and-test process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182920 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r182909.Evgeniy Stepanov2013-05-303-258/+0
| | | | | | | PR/16177 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182919 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix warning on varialbe unused in opt builds.Daniel Jasper2013-05-301-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182914 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed bug when tests in executable partially used absolute paths.Galina Kistanova2013-05-301-3/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182910 91177308-0d34-0410-b5e6-96231b3b80d8
* Swizzle vector inputs if it helps us eliminate shuffles.Nick Lewycky2013-05-303-0/+258
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182909 91177308-0d34-0410-b5e6-96231b3b80d8
* Change how we iterate over relocations on ELF.Rafael Espindola2013-05-3083-339/+423
| | | | | | | | | | | | | | | | | | | | | | | | | | For COFF and MachO, sections semantically have relocations that apply to them. That is not the case on ELF. In relocatable objects (.o), a section with relocations in ELF has offsets to another section where the relocations should be applied. In dynamic objects and executables, relocations don't have an offset, they have a virtual address. The section sh_info may or may not point to another section, but that is not actually used for resolving the relocations. This patch exposes that in the ObjectFile API. It has the following advantages: * Most (all?) clients can handle this more efficiently. They will normally walk all relocations, so doing an effort to iterate in a particular order doesn't save time. * llvm-readobj now prints relocations in the same way the native readelf does. * probably most important, relocations that don't point to any section are now visible. This is the case of relocations in the rela.dyn section. See the updated relocation-executable.test for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182908 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename variable to be more descriptive.Eric Christopher2013-05-301-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182903 91177308-0d34-0410-b5e6-96231b3b80d8
* Formatting.Eric Christopher2013-05-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182902 91177308-0d34-0410-b5e6-96231b3b80d8
* Reformat comments here.Eric Christopher2013-05-301-26/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182901 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a comment and some tests including the NULL byte.Eric Christopher2013-05-301-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182900 91177308-0d34-0410-b5e6-96231b3b80d8
* This testcase tests command line attributes which we don't yet support.Bill Wendling2013-05-301-62/+0
| | | | | | | | In fact, we're probably going to support these flags in completely different ways. So this test is no longer valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182899 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead return.Rafael Espindola2013-05-301-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182898 91177308-0d34-0410-b5e6-96231b3b80d8
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