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* Sphinxify the exception handling doc.Bill Wendling2012-06-273-564/+369
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159254 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence uninitialized variable warning in MipsISelDAGToDAG.cpp.Akira Hatanaka2012-06-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159243 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r159240.Akira Hatanaka2012-06-271-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159242 91177308-0d34-0410-b5e6-96231b3b80d8
* Exclude both libcxx and compiler-rt until we get their CMake buildsChandler Carruth2012-06-271-1/+2
| | | | | | suitable for building as a whole-project. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159241 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug in computation of stack size in MipsFrameLowering.cpp.Akira Hatanaka2012-06-272-3/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159240 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce indentation in function. Rearrange some methods. No functionality change.Bill Wendling2012-06-261-223/+222
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159239 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: AsmMatcher diagnostics preference detail.Jim Grosbach2012-06-261-1/+3
| | | | | | | Don't override a custom diagnostic w/ a generic InvalidOperand, all else being equal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159238 91177308-0d34-0410-b5e6-96231b3b80d8
* Revamp how debugging information is emitted for debug info objects.Bill Wendling2012-06-262-196/+113
| | | | | | | | | | It's not necessary for each DI class to have its own copy of `print' and `dump'. Instead, just give DIDescriptor those methods and have it call the appropriate debugging printing routine based on the type of the debug information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159237 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a missing check to avoid dereference null. No sensible test case ↵Evan Cheng2012-06-261-0/+2
| | | | | | possible. Sorry. rdar://11745134 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159236 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a instcombine transform that (no longer?) makes sense:Evan Cheng2012-06-263-33/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | // C - zext(bool) -> bool ? C - 1 : C if (ZExtInst *ZI = dyn_cast<ZExtInst>(Op1)) if (ZI->getSrcTy()->isIntegerTy(1)) return SelectInst::Create(ZI->getOperand(0), SubOne(C), C); This ends up forming sext i1 instructions that codegen to terrible code. e.g. int blah(_Bool x, _Bool y) { return (x - y) + 1; } => movzbl %dil, %eax movzbl %sil, %ecx shll $31, %ecx sarl $31, %ecx leal 1(%rax,%rcx), %eax ret Without the rule, llvm now generates: movzbl %sil, %ecx movzbl %dil, %eax incl %eax subl %ecx, %eax ret It also helps with ARM (and pretty much any target that doesn't have a sext i1 :-). The transformation was done as part of Eli's r75531. He has given the ok to remove it. rdar://11748024 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159230 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement getHostCPUName for ARM/linux. This will be used to implement ↵Benjamin Kramer2012-06-261-0/+55
| | | | | | | | | | -march=native in clang. The cpuid registers are only available in privileged mode so we don't have an OS-independent way of implementing this. ARM doesn't provide a list of processor IDs so the list is somewhat incomplete. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159228 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix llc's -print-before=pass and -print-after=pass.Rafael Espindola2012-06-262-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159227 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-2613-4/+268
| | | | | | | | | | | | | Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach TableGen to put chains on more instructionsTim Northover2012-06-261-0/+7
| | | | | | | | | | | | When generating selection tables for Pat instances, TableGen relied on an output Instruction's Pattern field being set to infer whether a chain should be added. This patch adds additional logic to check various flag fields so that correct code can be generated even if Pattern is unset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159217 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ThreadLocalImpl::getInstance for --disable-threads.Argyrios Kyrtzidis2012-06-261-3/+5
| | | | | | PR13114. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159210 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow targets to inject passes before the virtual register rewriter.Jakob Stoklund Olesen2012-06-262-1/+17
| | | | | | | | Such passes can be used to tweak the register assignments in a target-dependent way, for example to avoid write-after-write dependencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159209 91177308-0d34-0410-b5e6-96231b3b80d8
* IntegersSubsetTest: Due to compilation failure with -std=c11, replaced -1UL ↵Stepan Dyatkovskiy2012-06-261-4/+8
| | | | | | with NOT_A_NUMBER constant (0xffff). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159207 91177308-0d34-0410-b5e6-96231b3b80d8
* There are a number of generic inline asm operand modifiers thatJack Carter2012-06-2610-12/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | up to r158925 were handled as processor specific. Making them generic and putting tests for these modifiers in the CodeGen/Generic directory caused a number of targets to fail. This commit addresses that problem by having the targets call the generic routine for generic modifiers that they don't currently have explicit code for. For now only generic print operands 'c' and 'n' are supported.vi Affected files: test/CodeGen/Generic/asm-large-immediate.ll lib/Target/PowerPC/PPCAsmPrinter.cpp lib/Target/NVPTX/NVPTXAsmPrinter.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/XCore/XCoreAsmPrinter.cpp lib/Target/X86/X86AsmPrinter.cpp lib/Target/Hexagon/HexagonAsmPrinter.cpp lib/Target/CellSPU/SPUAsmPrinter.cpp lib/Target/Sparc/SparcAsmPrinter.cpp lib/Target/MBlaze/MBlazeAsmPrinter.cpp lib/Target/Mips/MipsAsmPrinter.cpp MSP430 isn't represented because it did not even run with the long existing 'c' modifier and it was not apparent what needs to be done to get it inline asm ready. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159203 91177308-0d34-0410-b5e6-96231b3b80d8
* Replacing zero-sized alloca's with a null pointer is too aggressive, insteadDuncan Sands2012-06-262-9/+47
| | | | | | | | | | | | | | | | | merge all zero-sized alloca's into one, fixing c43204g from the Ada ACATS conformance testsuite. What happened there was that a variable sized object was being allocated on the stack, "alloca i8, i32 %size". It was then being passed to another function, which tested that the address was not null (raising an exception if it was) then manipulated %size bytes in it (load and/or store). The optimizers cleverly managed to deduce that %size was zero (congratulations to them, as it isn't at all obvious), which made the alloca zero size, causing the optimizers to replace it with null, which then caused the check mentioned above to fail, and the exception to be raised, wrongly. Note that no loads and stores were actually being done to the alloca (the loop that does them is executed %size times, i.e. is not executed), only the not-null address check. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159202 91177308-0d34-0410-b5e6-96231b3b80d8
* IntegersSubsetMapping: implemented "diff" operation. Operation allows at the ↵Stepan Dyatkovskiy2012-06-262-3/+401
| | | | | | | | | | | | | | | same time perform up to three operations: - LHS exclude RHS - LHS intersect RHS (LHS successors will keeped) - RHS exclude LHS The complexity is N+M, where N is size of LHS M is size of RHS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159201 91177308-0d34-0410-b5e6-96231b3b80d8
* IntegersSubsetMapping: removed exclude operation, it will replaced with more ↵Stepan Dyatkovskiy2012-06-262-226/+0
| | | | | | | | | | universal "diff" operation in next commit. Changes was separated onto two commits for better readability. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159200 91177308-0d34-0410-b5e6-96231b3b80d8
* Sphyinxify the Bugpoint document.Bill Wendling2012-06-263-317/+220
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159199 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed unused variableElena Demikhovsky2012-06-261-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159197 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename to match other X86_64* names.Bill Wendling2012-06-263-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159196 91177308-0d34-0410-b5e6-96231b3b80d8
* Shuffle optimization for AVX/AVX2.Elena Demikhovsky2012-06-262-0/+73
| | | | | | | | | | | | | | | | | | | | The current patch optimizes frequently used shuffle patterns and gives these instruction sequence reduction. Before: vshufps $-35, %xmm1, %xmm0, %xmm2 ## xmm2 = xmm0[1,3],xmm1[1,3] vpermilps $-40, %xmm2, %xmm2 ## xmm2 = xmm2[0,2,1,3] vextractf128 $1, %ymm1, %xmm1 vextractf128 $1, %ymm0, %xmm0 vshufps $-35, %xmm1, %xmm0, %xmm0 ## xmm0 = xmm0[1,3],xmm1[1,3] vpermilps $-40, %xmm0, %xmm0 ## xmm0 = xmm0[0,2,1,3] vinsertf128 $1, %xmm0, %ymm2, %ymm0 After: vshufps $13, %ymm0, %ymm1, %ymm1 ## ymm1 = ymm1[1,3],ymm0[0,0],ymm1[5,7],ymm0[4,4] vshufps $13, %ymm0, %ymm0, %ymm0 ## ymm0 = ymm0[1,3,0,0,5,7,4,4] vunpcklps %ymm1, %ymm0, %ymm0 ## ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159188 91177308-0d34-0410-b5e6-96231b3b80d8
* Update a bunch of stale comments that dated from when this folled theChandler Carruth2012-06-261-14/+11
| | | | | | | very first (and worst) placement algorithm. These should now more accurately reflect the reality of the pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159185 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some duplicate instructions that exist only to given different ↵Craig Topper2012-06-263-28/+25
| | | | | | mnemonics for the assembler. Use InstAlias instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159184 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable the new LoopInfo algorithm by default.Andrew Trick2012-06-2610-244/+52
| | | | | | | | | | | | | | | | | | | | | | | | The primary advantage is that loop optimizations will be applied in a stable order. This helps debugging and unit test creation. It is also a better overall implementation without pathologically bad performance on deep functions. On large functions (llvm-stress --size=200000 | opt -loops) Before: 0.1263s After: 0.0225s On deep functions (after tweaking llvm-stress, thanks Nadav): Before: 0.2281s After: 0.0227s See r158790 for more comments. The loop tree is now consistently generated in forward order, but loop passes are applied in reverse order over the program. If we have a loop optimization that prefers forward order, that can easily be achieved by adding a different type of LoopPassManager. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159183 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary FIXMEAndrew Trick2012-06-261-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159182 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure type is not extended or untyped before create a constant of the ↵Evan Cheng2012-06-261-0/+4
| | | | | | type. No test case. Found by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159179 91177308-0d34-0410-b5e6-96231b3b80d8
* Typo.Eric Christopher2012-06-261-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159178 91177308-0d34-0410-b5e6-96231b3b80d8
* Make some ugly hacks for inline asm operands which name a specific register ↵Eli Friedman2012-06-252-5/+21
| | | | | | a bit more thorough. PR13196. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159176 91177308-0d34-0410-b5e6-96231b3b80d8
* revert my previous commit (r159173), since as Eli pointed out, it's ↵Nuno Lopes2012-06-252-1/+2
| | | | | | perfectly ok to mark realloc as noalias git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159175 91177308-0d34-0410-b5e6-96231b3b80d8
* do not set realloc() as NotAlias, since it can return the same pointer. This ↵Nuno Lopes2012-06-252-2/+1
| | | | | | whole thing should be upgraded to use the MemoryBuiltin interface anyway.. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159173 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: update peephole optimization.Manman Ren2012-06-252-2/+30
| | | | | | | | | | | | More condition codes are included when deciding whether to remove cmp after a sub instruction. Specifically, we extend from GE|LT|GT|LE to GE|LT|GT|LE|HS|LS|HI|LO|EQ|NE. If we have "sub a, b; cmp b, a; movhs", we should be able to replace with "sub a, b; movls". rdar: 11725965 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159166 91177308-0d34-0410-b5e6-96231b3b80d8
* Define DAGOperand, an empty base class for RegisterClass and Operand. This ↵Owen Anderson2012-06-251-2/+9
| | | | | | allows one to write multiclasses that are polymorphic over both registers and non-register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159162 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the objc_autoreleasedReturnValue optimization code to locateDan Gohman2012-06-252-6/+48
| | | | | | | | the call correctly even in the case where it is an invoke. This fixes rdar://11714057. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159157 91177308-0d34-0410-b5e6-96231b3b80d8
* Enforce stricter liveness rules for PHIs.Jakob Stoklund Olesen2012-06-252-6/+37
| | | | | | | | | | | | | Verify that all paths from the entry block to a virtual register read pass through a def. Enable this check even when MRI->isSSA() is false. Verify that the live range of a virtual register is live out of all predecessor blocks, even for PHI-values. This requires that PHIElimination sometimes inserts IMPLICIT_DEF instruction in predecessor blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159150 91177308-0d34-0410-b5e6-96231b3b80d8
* Run ProcessImplicitDefs on SSA form where it can be much simpler.Jakob Stoklund Olesen2012-06-253-264/+101
| | | | | | | | | | | Implicitly defined virtual registers can simply have the <undef> bit set on all uses, and copies can be turned into implicit defs recursively. Physical registers are a bit trickier. We handle the common case where a physreg def is used by a nearby instruction in the same basic block. For more complicated cases, just leave the IMPLICIT_DEF instruction in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159149 91177308-0d34-0410-b5e6-96231b3b80d8
* improve optimization of invoke instructions:Nuno Lopes2012-06-255-5/+63
| | | | | | | | - simplifycfg: invoke undef/null -> unreachable - instcombine: invoke new -> invoke expect(0, 0) (an arbitrary NOOP intrinsic; only done if the allocated memory is unused, of course) - verifier: allow invoke of intrinsics (to make the previous step work) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159146 91177308-0d34-0410-b5e6-96231b3b80d8
* check for the NoAlias attribute through CallSiteNuno Lopes2012-06-251-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159145 91177308-0d34-0410-b5e6-96231b3b80d8
* add CallSite/CallInst/InvokeInst::hasFnAttr()Nuno Lopes2012-06-252-11/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159144 91177308-0d34-0410-b5e6-96231b3b80d8
* PR13013: ELF Type identification fails for MSB type ELF files.Meador Inge2012-06-252-2/+16
| | | | | | | | | | Fix 'sys::IdentifyFileType' to work with big and little endian byte orderings when reading the ELF object file type. Initial patch by Stefan Hepp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159138 91177308-0d34-0410-b5e6-96231b3b80d8
* If a constant or a function has linkonce_odr linkage and unnamed_addr, mark itRafael Espindola2012-06-253-0/+31
| | | | | | | | hidden. Being linkonce_odr guarantees that it is available in every dso that needs it. Being a constant/function with unnamed_addr guarantees that the copies don't have to be merged. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159136 91177308-0d34-0410-b5e6-96231b3b80d8
* The name (and comment describing) of llvm::GetFirstDebuigLocInBasicBlock no ↵Eli Bendersky2012-06-253-15/+5
| | | | | | longer represents what the function does. Therefore, the function is removed and its functionality is folded into the only place in the code-base where it was being used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159133 91177308-0d34-0410-b5e6-96231b3b80d8
* Add SSE2 predicate to CVTPS2PD instructions. Doesn't matter much because ↵Craig Topper2012-06-251-0/+3
| | | | | | there are no patterns in the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159127 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove codegen only instruction in favor of one that has the same ↵Craig Topper2012-06-252-13/+10
| | | | | | definition. Make some pattern operands more explicit about types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159126 91177308-0d34-0410-b5e6-96231b3b80d8
* Just remove generic support for C++11 alignas -- GCC is alreadyChandler Carruth2012-06-251-1/+1
| | | | | | | | advertising complete support w/o alignas implemented, and its implementation of alignas in the latest versions is so convoluted as to be unusable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159125 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach PHIElimination to handle <undef> operands.Jakob Stoklund Olesen2012-06-251-19/+34
| | | | | | | | | When a PHI use is <undef>, don't emit a copy in the predecessor block, but insert an IMPLICIT_DEF instruction instead. This ensures that virtual register uses are always jointly dominated by defs, even if some of them are IMPLICIT_DEF. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159121 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle <undef> operands in TwoAddressInstructionPass.Jakob Stoklund Olesen2012-06-251-12/+31
| | | | | | | | | | | | | | | | | When the source register to a 2-addr instruction is undefined, there is no need to attempt any transformations - simply replace the source register with the destination register. This also comes up when lowering IMPLICIT_DEF instructions - make sure the <undef> flag is moved to the new partial register def operand: %vreg8<def> = INSERT_SUBREG %vreg9<undef>, %vreg0<kill>, sub_16bit rewrite undef: %vreg8<def> = INSERT_SUBREG %vreg8<undef>, %vreg0<kill>, sub_16bit convert to: %vreg8:sub_16bit<def,read-undef> = COPY %vreg0<kill> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159120 91177308-0d34-0410-b5e6-96231b3b80d8
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