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* The LIT tests below do not specify the exact cpu model and fail on AVX2 ↵Nadav Rotem2012-07-125-9/+9
| | | | | | | | | | machines, because we select different instructions such as vbroadcast, new shuffles, etc. Patch by Michael Liao. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160129 91177308-0d34-0410-b5e6-96231b3b80d8
* detabifyGabor Greif2012-07-121-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160128 91177308-0d34-0410-b5e6-96231b3b80d8
* fix typo in generated commentGabor Greif2012-07-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160127 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/X86/rdrand.ll: Relax expression corresponding to Win64 CC.NAKAMURA Takumi2012-07-121-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160124 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CMakeLists.txt: Add llvm-diff to deps.NAKAMURA Takumi2012-07-121-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160123 91177308-0d34-0410-b5e6-96231b3b80d8
* Use %s instead of the explicit name, the latter doesn't work in out-of-tree ↵Benjamin Kramer2012-07-121-1/+1
| | | | | | builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160120 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsics for Ivy Bridge's rdrand instruction.Benjamin Kramer2012-07-125-3/+107
| | | | | | | | | The rdrand/cmov sequence is the same that is emitted by both GCC and ICC. Fixes PR13284. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160117 91177308-0d34-0410-b5e6-96231b3b80d8
* The result type of EXTRACT_VECTOR_ELT doesn't have to match the element type ofDuncan Sands2012-07-122-0/+30
| | | | | | | | | | the input vector, it can be bigger (this is helpful for powerpc where <2 x i16> is a legal vector type but i16 isn't a legal type, IIRC). However this wasn't being taken into account by ExpandRes_EXTRACT_VECTOR_ELT, causing PR13220. Lightly tweaked version of a patch by Michael Liao. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160116 91177308-0d34-0410-b5e6-96231b3b80d8
* Update GATHER instructions to support 2 read-write operands. Patch from ↵Craig Topper2012-07-127-30/+77
| | | | | | myself and Manman Ren. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160110 91177308-0d34-0410-b5e6-96231b3b80d8
* Instcombine was transforming:Evan Cheng2012-07-122-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | %shr = lshr i64 %key, 3 %0 = load i64* %val, align 8 %sub = add i64 %0, -1 %and = and i64 %sub, %shr ret i64 %and to: %shr = lshr i64 %key, 3 %0 = load i64* %val, align 8 %sub = add i64 %0, 2305843009213693951 %and = and i64 %sub, %shr ret i64 %and The demanded bit optimization is actually a pessimization because add -1 would be codegen'ed as a sub 1. Teach the demanded constant shrinking optimization to check for negated constant to make sure it is actually reducing the width of the constant. rdar://11793464 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160101 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Location information for diagnostic.Jim Grosbach2012-07-121-1/+1
| | | | | | | | | | | def Pat<...>; Results in 'record name is not a string!' diagnostic. Not the best, but the lack of location information moves it from not very helpful into completely useless. We're in the Record class when throwing the error, so just add the location info directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160098 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix typo in commentsManman Ren2012-07-111-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160093 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix optimizeCompare to correctly check safe condition.Manman Ren2012-07-112-9/+33
| | | | | | | | | It is safe if CPSR is killed or re-defined. When we are done with the basic block, check whether CPSR is live-out. Do not optimize away cmp if CPSR is live-out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160090 91177308-0d34-0410-b5e6-96231b3b80d8
* Patch for Mips direct object generation.Jack Carter2012-07-111-0/+8
| | | | | | | | | | | | | | | | | | When WriteFragmentData() case FT_align called Asm.getBackend().writeNopData() is called, nothing is done since Mips implementation of writeNopData just returned "true". For some reason this has not caused problems in 32 bit mode, but in 64 bit mode it caused an assert when processing multiple function units. The test case included will assert without this patch. It runs twice with different flags to prevent false positives due to changes in code generation over time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160084 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixup broken doc link. Patch by Sean Silva <silvas@purdue.edu>.Chad Rosier2012-07-112-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160082 91177308-0d34-0410-b5e6-96231b3b80d8
* This change removes an "initialization" warning.Jack Carter2012-07-111-4/+3
| | | | | | | | | Even though variable in question could not be initialized before use, the code was such that the compiler had no way of knowing that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160081 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed diff comparison.Stepan Dyatkovskiy2012-07-111-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160076 91177308-0d34-0410-b5e6-96231b3b80d8
* In MemoryBuffer::getOpenFile() don't verify that the mmap'edArgyrios Kyrtzidis2012-07-111-10/+0
| | | | | | | | | | | | file buffer is null-terminated. If the file is smaller than we thought, mmap will not allow dereferencing past the pages that are enough to cover the actual file size, even though we asked for a larger address range. rdar://11612916 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160075 91177308-0d34-0410-b5e6-96231b3b80d8
* In register classes in MipsRegisterInfo.td, list the registers in ascendingAkira Hatanaka2012-07-111-99/+114
| | | | | | | | | | order of binary encoding. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160073 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86 fast-isel] Per discussion with Eric, add all cases to switch with verboseChad Rosier2012-07-111-1/+8
| | | | | | | | comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160069 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r160036.Akira Hatanaka2012-07-111-0/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160067 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Update to peephole optimization to move Movr0 before (Sub, Cmp) pair.Manman Ren2012-07-112-1/+34
| | | | | | | | When Movr0 is between sub and cmp, we move Movr0 before sub if it enables removal of Cmp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160066 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.Akira Hatanaka2012-07-113-3/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160064 91177308-0d34-0410-b5e6-96231b3b80d8
* InstrEmitter::EmitSubregNode() optimize extract_subreg in this case:Evan Cheng2012-07-111-1/+2
| | | | | | | | | | | | | | | | | | r1025 = s/zext r1024, 4 r1026 = extract_subreg r1025, 4 to a copy: r1026 = copy r1024 This is correct. However it uses TII->isCoalescableExtInstr() which can return true for instructions which essentially does a sext_in_reg so this can end up with an illegal copy where the source and destination register classes do not match. Add a check to avoid it. Sorry, no test case possible at this time. rdar://11849816 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160059 91177308-0d34-0410-b5e6-96231b3b80d8
* PR13326: Fix a subtle edge case in the udiv -> magic multiply generator.Benjamin Kramer2012-07-112-1/+22
| | | | | | This caused 6 of 65k possible 8 bit udivs to be wrong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160058 91177308-0d34-0410-b5e6-96231b3b80d8
* test commitTom Stellard2012-07-111-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160056 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86 fast-isel] Rather then call llvm_unreachable() have fast-isel fall backChad Rosier2012-07-111-1/+1
| | | | | | to Selection DAG isel. Patch by Andrew Kaylor <andrew.kaylor@intel.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160055 91177308-0d34-0410-b5e6-96231b3b80d8
* When ext-loading and trunc-storing vectors to memory, on x86 32bit systems, ↵Nadav Rotem2012-07-116-11/+38
| | | | | | allow loads/stores of 64bit values from xmm registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160044 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename many of the Tmp1, Tmp2, Tmp3 variables to names such as Chain, Value, ↵Nadav Rotem2012-07-111-100/+104
| | | | | | | | | | Ptr, etc. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160042 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused variable.Benjamin Kramer2012-07-111-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160040 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor the DAG Legalizer by extracting the legalization ofNadav Rotem2012-07-111-422/+434
| | | | | | | | | Load and Store nodes into their own functions. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160037 91177308-0d34-0410-b5e6-96231b3b80d8
* Only apply the SETCC+SITOFP -> SELECTCC optimization when the SETCC returns ↵Owen Anderson2012-07-111-1/+2
| | | | | | | | | an MVT::i1, i.e. before type legalization. This is a speculative fix for a problem on Mips reported by Akira Hatanaka. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160036 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower RETURNADDR node in Mips backend.Akira Hatanaka2012-07-114-5/+54
| | | | | | | Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160031 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips specific inline asm operand modifier 'L'.Jack Carter2012-07-102-15/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Low order register of a double word register operand. Operands are defined by the name of the variable they are marked with in the inline assembler code. This is a way to specify that the operand just refers to the low order register for that variable. It is the opposite of modifier 'D' which specifies the high order register. Example: main() { long long ll_input = 0x1111222233334444LL; long long ll_val = 3; int i_result = 0; __asm__ __volatile__( "or %0, %L1, %2" : "=r" (i_result) : "r" (ll_input), "r" (ll_val)); } Which results in: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -8 addu $2, $2, $25 sw $2, 0($sp) lui $2, 13107 ori $3, $2, 17476 <-- Low 32 bits of ll_input lui $2, 4369 ori $4, $2, 8738 <-- High 32 bits of ll_input addiu $5, $zero, 3 <-- Low 32 bits of ll_val addiu $2, $zero, 0 <-- High 32 bits of ll_val #APP or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val #NO_APP addiu $sp, $sp, 8 jr $ra If not direction is done for the long long for 32 bit variables results in using the low 32 bits as ll_val shows. There is an existing bug if 'L' or 'D' is used for the destination register for 32 bit long longs in that the target value will be updated incorrectly for the non-specified part unless explicitly set within the inline asm code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
* Require and preserve LoopInfo for early if-conversion.Jakob Stoklund Olesen2012-07-101-0/+17
| | | | | | It will surely be needed by heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160027 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the LiveInterval::join function to use the fast merge algorithm,Chandler Carruth2012-07-102-15/+18
| | | | | | | | | | | generalizing its implementation sufficiently to support this value number scenario as well. This cuts out another significant performance hit in large functions (over 10k basic blocks, etc), especially those with "natural" CFG structures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160026 91177308-0d34-0410-b5e6-96231b3b80d8
* Run early if-conversion in domtree post-order.Jakob Stoklund Olesen2012-07-101-49/+60
| | | | | | | | | | | This ordering allows nested if-conversion without using a work list, and it makes it possible to update the dominator tree on the fly as well. Any erased basic blocks will always be dominated by the current post-order position, so the domtree can be pruned without invalidating the iterator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160025 91177308-0d34-0410-b5e6-96231b3b80d8
* Move [get|set]BasePtrStackAdjustment() from MachineFrameInfo toChad Rosier2012-07-103-19/+19
| | | | | | | | X86MachineFunctionInfo as this is currently only used by X86. If this ever becomes an issue on another arch (e.g., ARM) then we can hoist it back out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160009 91177308-0d34-0410-b5e6-96231b3b80d8
* Add newline.Chad Rosier2012-07-101-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160006 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test case accidentally omitted from r160002.Chad Rosier2012-07-101-0/+242
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160004 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for dynamic stack realignment in the presence of dynamic allocas onChad Rosier2012-07-107-19/+139
| | | | | | | | | | | | | | X86. Basically, this is a reapplication of r158087 with a few fixes. Specifically, (1) the stack pointer is restored from the base pointer before popping callee-saved registers and (2) in obscure cases (see comments in patch) we must cache the value of the original stack adjustment in the prologue and apply it in the epilogue. rdar://11496434 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160002 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug where I didn't test for an empty range before inspecting theChandler Carruth2012-07-101-1/+2
| | | | | | | | | | | | | | | back of it. I don't have anything even remotely close to a test case for this. It only broke two build bots, both of them doing bootstrap builds, one of them a dragonegg bootstrap. It doesn't break for me when I bootstrap either. It doesn't reproduce every time or on many machines during the bootstrap. Many thanks to Duncan Sands who got the exact command (and stage of the bootstrap) which failed on the dragonegg bootstrap and managed to get it to trigger under valgrind with debug symbols. The fix was then found by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159993 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve the loading of load-anyext vectors by allowing the codegen to loadNadav Rotem2012-07-105-40/+73
| | | | | | | | | | | multiple scalars and insert them into a vector. Next, we shuffle the elements into the correct places, as before. Also fix a small dagcombine bug in SimplifyBinOpWithSameOpcodeHands, when the migration of bitcasts happened too late in the SelectionDAG process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159991 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-104-9/+49
| | | | | | single-precision resiters) (and do it properly this time! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverse assembler/disassembler operand order for gather instructions.Craig Topper2012-07-103-52/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159983 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an efficient merge operation to LiveInterval and use it to avoidChandler Carruth2012-07-102-32/+135
| | | | | | | | | | | quadratic behavior when performing pathological merges. Fixes the core element of PR12652. There is only one user of addRangeFrom left: join. I'm hoping to refactor further in a future patch and have join use this merge operation as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159982 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach LiveIntervals how to verify themselves and start using it in someChandler Carruth2012-07-102-0/+42
| | | | | | | | | | of the trick merge routines. This adds a layer of testing that was necessary when implementing more efficient (and complex) merge logic for this datastructure. No functionality changed here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159981 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Allow more flexible patterns in NEON formats.Jim Grosbach2012-07-101-53/+53
| | | | | | | | | Some NEON instructions want to match against normal SDNodes for some operand types and Intrinsics for others. For example, CTLZ. To enable this, switch from explicitly requiring Intrinsic on the class templates to using SDPatternOperator instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159974 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow intrinsics to be used in place of node matchables.Jim Grosbach2012-07-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | TableGen has support for using an intrinics name directly in a DAG, but this breaks down when referring to just a node, as that's handled initializer list stuff entirely via subclassing in the parser. That is, using an instrinsic like "(int_my_intrinsic ...)" works fine. Using it standalone for parameterizing the operator in such a DAG does not. Fixing this is simple enough, as we simply declare Intrinsic as deriving from SDPatternOperator, which is the class name intended for exactly this purpose in TargetSelectionDAG.td. When the intrinsic is actually used in the DAG pattern, it will be recognized and expanded to an intrinsic_wo_chain (et. al.) just like when it's used directly. Incoming ARM NEON cleanup based on this and a bit of functionality improvement after that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159973 91177308-0d34-0410-b5e6-96231b3b80d8
* Make register Mips::RA allocatable if not in mips16 mode.Akira Hatanaka2012-07-1010-37/+376
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159971 91177308-0d34-0410-b5e6-96231b3b80d8
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