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* Remove default copy ctor/assignment, makes AttributeSet trivially copyable.Benjamin Kramer2013-03-181-5/+0
| | | | | | And enables SmallVector's pod optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177281 91177308-0d34-0410-b5e6-96231b3b80d8
* Initially forgotten-to-svn-add test case for r177279.David Tweed2013-03-181-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177280 91177308-0d34-0410-b5e6-96231b3b80d8
* The optimization a + (-0.0f) -> a was being misapplied to a + (+0.0f) in ↵David Tweed2013-03-181-0/+13
| | | | | | | | | | | | the vector case (because we weren't differntiating floating-point zeroinitializers from other zero-initializers) which was causing problems for code relying upon a + (+0.0f) to, eg, flush denormals to 0. Make the scalar and vector cases have the same behaviour. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177279 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: implement indirect adressing for SIChristian Konig2013-03-183-1/+190
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177277 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: add float vector typesChristian Konig2013-03-184-21/+82
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177276 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: add shl patternChristian Konig2013-03-183-1/+8
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177275 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: add BUFFER_LOAD_DWORD patternChristian Konig2013-03-181-3/+9
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177274 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: implement SI.load.const intrinsicChristian Konig2013-03-182-2/+13
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177273 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: enable all S_LOAD and S_BUFFER_LOAD opcodesChristian Konig2013-03-182-14/+29
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177272 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: fix inserting waits for all definesChristian Konig2013-03-181-15/+1
| | | | | | | | | | | Unfortunately the previous fix for inserting waits for unordered defines wasn't sufficient, cause it's possible that even ordered defines are only partially used (or not used at all). Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177271 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] when creating string constants, set unnamed_attr and align 1 so that ↵Kostya Serebryany2013-03-182-3/+7
| | | | | | equal strings are merged by the linker. Observed up to 1% binary size reduction. Thanks to Anton Korobeynikov for the suggestion git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177264 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark internal classes as POD-like to get better behavior out ofChandler Carruth2013-03-181-102/+109
| | | | | | | | SmallVector and DenseMap. This speeds up SROA by 25% on PR15412. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177259 91177308-0d34-0410-b5e6-96231b3b80d8
* TLS support for MinGW targets.Anton Korobeynikov2013-03-181-7/+8
| | | | | | | | | MinGW is almost completely compatible to MSVC, with the exception of the _tls_array global not being available. Patch by David Nadlinger! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177257 91177308-0d34-0410-b5e6-96231b3b80d8
* Windows TLS: Section name prefix to ensure correct orderAnton Korobeynikov2013-03-181-2/+5
| | | | | | | | | | | | | The linker sorts the .tls$<xyz> sections by name, and we need to make sure any extra sections we produce (e.g. for weak globals) always end up between .tls$AAA and .tls$ZZZ, even if the name starts with e.g. an underscore. Patch by David Nadlinger! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177256 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] while generating the description of a global variable, emit the ↵Kostya Serebryany2013-03-181-7/+8
| | | | | | module name in a separate field, thus not duplicating this information if every description. This decreases the binary size (observed up to 3%). https://code.google.com/p/address-sanitizer/issues/detail?id=168 . This changes the asan API version. llvm-part git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177254 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] don't instrument functions with available_externally linkage. This ↵Kostya Serebryany2013-03-182-0/+13
| | | | | | saves a bit of compile time and reduces the number of redundant global strings generated by asan (https://code.google.com/p/address-sanitizer/issues/detail?id=167) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177250 91177308-0d34-0410-b5e6-96231b3b80d8
* Extract a method.Jakob Stoklund Olesen2013-03-182-41/+42
| | | | | | | This computes the type of an instruction operand or result based on the records in the instruction's ins and outs lists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177244 91177308-0d34-0410-b5e6-96231b3b80d8
* Post process ADC/SBB and use a shorter encoding if they use a sign extended ↵Craig Topper2013-03-182-0/+20
| | | | | | immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177243 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor some duplicated code into helper functions.Craig Topper2013-03-182-229/+62
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177242 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the build broken in r177239David Blaikie2013-03-171-1/+1
| | | | | | Seems some accidental C++11 crept in there. Reported by the C++98 buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177241 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduced dont-infinite-loop-during-block-escape-analysis.ll with bugpoint and ↵Michael Gottesman2013-03-172-87/+27
| | | | | | | | | | moved it to retain-block-escape-analysis.ll. *NOTE* I verified that the original bug behind dont-infinite-loop-during-block-escape-analysis.ll occurs when using opt on retain-block-escape-analysis.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177240 91177308-0d34-0410-b5e6-96231b3b80d8
* Split out filename & directory from DIFile to start generalizing over DIScopesDavid Blaikie2013-03-1787-220/+330
| | | | | | | | | | This is the first step to making all DIScopes have a common metadata prefix (so that things (using directives, for example) that can appear in any scope can be added to that common prefix). DIFile is itself a DIScope so the common prefix of all DIScopes cannot be a DIFile - instead it's the raw filename/directory name pair. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177239 91177308-0d34-0410-b5e6-96231b3b80d8
* Generalize debug info test to be resilient to changes in metadata node numberingDavid Blaikie2013-03-171-3/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177238 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve DIFile debug info annotation by letting it fallback to DIScopeDavid Blaikie2013-03-171-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177236 91177308-0d34-0410-b5e6-96231b3b80d8
* Use ArrayRef<MVT::SimpleValueType> when possible.Jakob Stoklund Olesen2013-03-176-10/+10
| | | | | | | Not passing vector references around makes it possible to use SmallVector in most places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177235 91177308-0d34-0410-b5e6-96231b3b80d8
* To avoid symbol clash, undefine PPC here. PPC may be predefined on some hosts.Sylvestre Ledru2013-03-173-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177234 91177308-0d34-0410-b5e6-96231b3b80d8
* Build LLVMgold.so on FreeBSD using cmake.Rafael Espindola2013-03-171-1/+2
| | | | | | Patch by Stephen Checkoway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177233 91177308-0d34-0410-b5e6-96231b3b80d8
* The promised test case for r175939.Michael Gottesman2013-03-171-0/+100
| | | | | | | | This test makes sure that the ObjCARC escape analysis looks at the uses of instructions which copy the block pointer value by checking all four cases where that can occur. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177232 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve PPC VR (Altivec) register spillingHal Finkel2013-03-176-42/+73
| | | | | | | | | | | | | | | | This change cleans up two issues with Altivec register spilling: 1. The spilling code was inefficient (using two instructions, and add and a load, when just one would do) 2. The code assumed that r0 would always be available (true for now, but this will change) The new code handles VR spilling just like GPR spills but forced into r+r mode. As a result, when any VR spills are present, we must now always allocate the register-scavenger spill slot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177231 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove FIXMEs in PPC test cases related to unaligned loads/storesHal Finkel2013-03-162-8/+0
| | | | | | | As pointed out by Bill in response to r177160, these two FIXMEs can also be removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177229 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove PPC avoidWriteAfterWrite callbackHal Finkel2013-03-162-16/+0
| | | | | | | | | As a follow-up to r158719, remove PPCRegisterInfo::avoidWriteAfterWrite. Jakob pointed out in response to r158719 that this callback is currently unused and so this has no effect (and the speedups that I thought that I had observed as a result of implementing this function must have been noise). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177228 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the default latency for implicit defs.Andrew Trick2013-03-161-1/+4
| | | | | | | | | | | | | | | | Implicit defs are not currently positional and not modeled by the per-operand machine model. Unfortunately, we treat defs that are part of the architectural instruction description, like flags, the same as other implicit defs. Really, they should have a fixed MachineInstr layout and probably shouldn't be "implicit" at all. For now, we'll change the default latency to be the max operand latency. That will give flag setting operands full latency for x86 folded loads. Other kinds of "fake" implicit defs don't occur prior to regalloc anyway, and we would like them to go away postRegAlloc as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177227 91177308-0d34-0410-b5e6-96231b3b80d8
* Machine model. Allow mixed itinerary classes and SchedRW lists.Andrew Trick2013-03-163-205/+174
| | | | | | | | | | | | | We always supported a mixture of the old itinerary model and new per-operand model, but it required a level of indirection to map itinerary classes to SchedRW lists. This was done for ARM A9. Now we want to define x86 SchedRW lists, with the goal of removing its itinerary classes, but still support the itineraries in the mean time. When I original developed the model, Atom did not have itineraries, so there was no reason to expect this requirement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177226 91177308-0d34-0410-b5e6-96231b3b80d8
* [docs] Discuss a potential bug to be aware of.Sean Silva2013-03-161-0/+72
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177224 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for graceful handling of long file names on Windows. Patch thanks ↵Aaron Ballman2013-03-161-0/+12
| | | | | | to Paul Robinson! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177223 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 code emitter support AVX encoded MRMDestReg instructions.Craig Topper2013-03-164-32/+94
| | | | | | | | Previously we weren't skipping the VVVV encoded register. Based on patch by Michael Liao. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177221 91177308-0d34-0410-b5e6-96231b3b80d8
* Define more SchedWrites for annotating X86 instructions.Jakob Stoklund Olesen2013-03-161-11/+57
| | | | | | | | | | | | | | Since almost all X86 instructions can fold loads, use a multiclass to define register/memory pairs of SchedWrites. An X86FoldableSchedWrite represents the register version of an instruction. It holds a reference to the SchedWrite to use when the instruction folds a load. This will be used inside multiclasses that define rr and rm instruction versions together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177210 91177308-0d34-0410-b5e6-96231b3b80d8
* Add SchedRW as an Instruction field.Jakob Stoklund Olesen2013-03-153-6/+14
| | | | | | | | | | | | | Don't require instructions to inherit Sched<...>. Sometimes it is more convenient to say: let SchedRW = ... in { ... } Which is now possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177199 91177308-0d34-0410-b5e6-96231b3b80d8
* [ADT] Fix StringSet::insert() to not allocate on every lookup.Daniel Dunbar2013-03-151-12/+14
| | | | | | | - The previous implementation always constructed the StringMap entry, even if the key was present in the set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177178 91177308-0d34-0410-b5e6-96231b3b80d8
* [Support][Path][Windows] Fix dangling else. Don't call CloseHandle when ↵Michael J. Spencer2013-03-151-10/+10
| | | | | | CloseFD is false. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177175 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM cost model: Fix costs for some vector selectsArnold Schwaighofer2013-03-153-116/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I was too pessimistic in r177105. Vector selects that fit into a legal register type lower just fine. I was mislead by the code fragment that I was using. The stores/loads that I saw in those cases came from lowering the conditional off an address. Changing the code fragment to: %T0_3 = type <8 x i18> %T1_3 = type <8 x i1> define void @func_blend3(%T0_3* %loadaddr, %T0_3* %loadaddr2, %T1_3* %blend, %T0_3* %storeaddr) { %v0 = load %T0_3* %loadaddr %v1 = load %T0_3* %loadaddr2 ==> FROM: ;%c = load %T1_3* %blend ==> TO: %c = icmp slt %T0_3 %v0, %v1 ==> USE: %r = select %T1_3 %c, %T0_3 %v0, %T0_3 %v1 store %T0_3 %r, %T0_3* %storeaddr ret void } revealed this mistake. radar://13403975 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177170 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding an A15 specific optimization pass for interactions between S/D/Q ↵Silviu Baranga2013-03-156-2/+777
| | | | | | registers. The pass handles all the required transformations pre-regalloc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177169 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix an old refacto.Benjamin Kramer2013-03-152-3/+13
| | | | | | Fixes PR15520. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177167 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable unaligned memory access on PPC for scalar typesHal Finkel2013-03-157-4/+110
| | | | | | | | | | | Unaligned access is supported on PPC for non-vector types, and is generally more efficient than manually expanding the loads and stores. A few of the existing test cases were using expanded unaligned loads and stores to test other features (like load/store with update), and for these test cases, unaligned access remains disabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177160 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM cost model: Fix cost of fptrunc and fpext instructionsArnold Schwaighofer2013-03-152-2/+41
| | | | | | | | A vector fptrunc and fpext simply gets split into scalar instructions. radar://13192358 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177159 91177308-0d34-0410-b5e6-96231b3b80d8
* Protect PPC Altivec patterns with a predicateHal Finkel2013-03-152-1/+7
| | | | | | | | | | | | In preparation for the addition of other SIMD ISA extensions (such as QPX) we need to make sure that all Altivec patterns are properly predicated on having Altivec support. No functionality change intended (one test case needed to be updated b/c it assumed that Altivec intrinsics would be supported without enabling Altivec support). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177152 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixup for r176933: more careful setup of path to llvm-symbolizerAlexey Samsonov2013-03-152-7/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177144 91177308-0d34-0410-b5e6-96231b3b80d8
* Use NumBaseBits in a few more places in SmallBitVector instead of ↵Craig Topper2013-03-151-6/+6
| | | | | | recalculating it. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177142 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the FDE encoding to be relative on ELF.Rafael Espindola2013-03-152-6/+17
| | | | | | | | | | | | This is a very late complement to r130637 which fixed this on x86_64. Fixes pr15448. Since it looks like that every elf architecture uses this encoding when using cfi, make it the default for elf. Just exclude mips64el. It has a lovely .ll -> .o test (ef_frame.ll) that tests that nothing changes in the binary content of the .eh_frame produced by llc. Oblige it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177141 91177308-0d34-0410-b5e6-96231b3b80d8
* Allocate the RS spill slot for any PPC function with spills and a large ↵Hal Finkel2013-03-156-38/+107
| | | | | | | | | | | | | | | | stack frame For spills into a large stack frame, the FI-elimination code uses the register scavenger to obtain a free GPR for use with an r+r-addressed load or store. When there are no available GPRs, the scavenger gets one by using its spill slot. Previously, we were not always allocating that spill slot and the RS would assert when the spill slot was needed. I don't currently have a small test that triggered the assert, but I've created a small regression test that verifies that the spill slot is now added when the stack frame is sufficiently large. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177140 91177308-0d34-0410-b5e6-96231b3b80d8
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