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| * Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach2011-06-309-86/+26
| * Add support for the 'h' constraint.Eric Christopher2011-06-303-1/+17
| * Add target a target hook to get the register number used by the compact unwindBill Wendling2011-06-304-0/+29
| * Revert my previous patch while I debug llvm-gcc bootstrap.Rafael Espindola2011-06-301-95/+10
| * Add one more comment to the FDE verbose asm output.Bill Wendling2011-06-301-0/+1
| * Don't give up on coalescing A and B when we findRafael Espindola2011-06-301-10/+95
| * Add a convenience typedef for std::pair<unsigned, const TargetRegisterClass*>.Eric Christopher2011-06-301-7/+8
| * Thumb1 register to register MOV instruction is predicable.Jim Grosbach2011-06-3010-59/+67
| * Add comments to the FDE.Bill Wendling2011-06-301-5/+13
| * Add more comments to the ASM output for the CIE's "moves".Bill Wendling2011-06-301-1/+20
| * Tweak error messages to match GCC. Should fix gcc.target/i386/pr30848.cJakob Stoklund Olesen2011-06-301-3/+3
| * Add comments to the ASM output to help understand the compact unwind and CIE ...Bill Wendling2011-06-301-6/+61
| * Create a isFullCopy predicate.Rafael Espindola2011-06-302-5/+4
| * Add r134057 back, but splice the predecessor after the successors phiRafael Espindola2011-06-305-11/+68
| * Pseudo-ize the Thumb tTPsoft instruction.Jim Grosbach2011-06-304-28/+7
| * indvars -disable-iv-rewrite: handle cloning binary operators that cannot over...Andrew Trick2011-06-302-7/+45
| * Pseudo-ize the t2LDMIA_RET instruction.Jim Grosbach2011-06-303-20/+13
| * Pseudo-ize the Thumb tPOP_RET instruction.Jim Grosbach2011-06-303-11/+12
| * Remove dead code.Rafael Espindola2011-06-301-88/+0
| * The enum was moved to ISDOpcodes.h.Duncan Sands2011-06-301-1/+1
| * Kill dead code.Jim Grosbach2011-06-301-1/+0
| * Size reducing SP adjusting t2ADDri needs to check predication.Jim Grosbach2011-06-301-1/+4
| * Fix ARMSubtarget feature parsing.Evan Cheng2011-06-301-10/+7
| * Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-3068-236/+271
| * Recognize the xstorerng alias for VIA PadLock's xstore instruction.Joerg Sonnenberger2011-06-302-0/+6
| * Reapply r134047 now that the world is ready for it.Jakob Stoklund Olesen2011-06-303-138/+291
| * indvars -disable-iv-rewrite: handle an edge case involving identity phis.Andrew Trick2011-06-302-10/+40
| * Remove getRegClassForInlineAsmConstraint and all dependencies.Eric Christopher2011-06-303-115/+0
| * Make sure we use the correct register class here since we'll need toEric Christopher2011-06-301-1/+2
| * Fix a small thinko for constant i64 lock/orq optimization where weEric Christopher2011-06-302-2/+22
| * * Use the proper size to output the range size.Bill Wendling2011-06-301-1/+8
| * Stupid error: If the LSDA and Personality functions aren't there, emit 0 insteadBill Wendling2011-06-291-10/+8
| * Revert r133953 for now.Devang Patel2011-06-294-148/+0
| * We don't want to use relocations inside the compact unwind section. Just use theBill Wendling2011-06-291-4/+19
| * Remove redundant Thumb2 ADD/SUB SP instruction definitions.Jim Grosbach2011-06-297-118/+56
| * Always adjust the stack pointer immediately after the call.Jakob Stoklund Olesen2011-06-291-0/+7
| * indvars -disable-iv-rewrite: insert new trunc instructions carefully.Andrew Trick2011-06-292-15/+52
| * Added IRBuilder::SetInsertPoint(Use) to find a valid insertion pointAndrew Trick2011-06-291-0/+19
| * whitespaceAndrew Trick2011-06-291-8/+8
| * In the ARM global merging pass, allow extraneous alignment specifiers. This passCameron Zwarich2011-06-292-2/+16
| * ARM RSCS* don't need explicit TableGen decoder checks.Jim Grosbach2011-06-291-4/+0
| * IndentationEvan Cheng2011-06-291-1/+1
| * Remove getRegClassForInlineAsmConstraint from the ARM port.Eric Christopher2011-06-292-59/+15
| * Remove todo.Eric Christopher2011-06-291-2/+0
| * make compose and isMoveInstr static functions.Rafael Espindola2011-06-292-16/+10
| * Refactor away tSpill and tRestore pseudos in ARM backend.Jim Grosbach2011-06-296-39/+9
| * Add a TODO for the Alpha port inline asm constraints.Eric Christopher2011-06-291-0/+2
| * Move Alpha from getRegClassForInlineAsmConstraint toEric Christopher2011-06-292-32/+14
| * Update comment for getRegForInlineAsmConstraint for Mips.Eric Christopher2011-06-291-3/+3
| * Move the Blackfin port away from getRegClassForInlineAsmConstraint byEric Christopher2011-06-293-29/+22
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