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* Cleanup whitespace.Bill Wendling2012-03-311-17/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153804 91177308-0d34-0410-b5e6-96231b3b80d8
* Free the codegen options when deleting LTO code generator object.Bill Wendling2012-03-311-26/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153803 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup whitespace and remove unneeded 'extern' keyword on function definitions.Bill Wendling2012-03-312-27/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153802 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up the naming in this test. Someone pointed this out in review atChandler Carruth2012-03-311-3/+3
| | | | | | one point, and I forgot to go back and clean it up. Sorry about that. =/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153801 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheck-ize this test, and generally tidy it up prior to changingChandler Carruth2012-03-311-21/+26
| | | | | | things around. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153799 91177308-0d34-0410-b5e6-96231b3b80d8
* I noticed in passing that the Metadata getIfExists method was creating a newDuncan Sands2012-03-312-4/+11
| | | | | | | node and returning it if one didn't exist. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153798 91177308-0d34-0410-b5e6-96231b3b80d8
* Correctly vectorize powi.Hal Finkel2012-03-312-11/+77
| | | | | | | | The powi intrinsic requires special handling because it always takes a single integer power regardless of the result type. As a result, we can vectorize only if the powers are equal. Fixes PR12364. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153797 91177308-0d34-0410-b5e6-96231b3b80d8
* comment typoAndrew Trick2012-03-311-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153796 91177308-0d34-0410-b5e6-96231b3b80d8
* Select static relocation model if it is jitting.Akira Hatanaka2012-03-311-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153795 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce Register Units: Give each leaf register a number.Andrew Trick2012-03-312-0/+60
| | | | | | | | First small step toward modeling multi-register multi-pressure. In the future, register units can also be used to model liveness and aliasing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153794 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a 2 byte safety margin in offset computations.Jakob Stoklund Olesen2012-03-311-2/+5
| | | | | | | | | | | | ARMConstantIslandPass still has bugs where jump table compression can cause constant pool entries to go out of range. Add a safety margin of 2 bytes when placing constant islands, but use the real max displacement for verification. <rdar://problem/11156595> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153789 91177308-0d34-0410-b5e6-96231b3b80d8
* Add more debugging output to ARMConstantIslandPass.Jakob Stoklund Olesen2012-03-311-2/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153788 91177308-0d34-0410-b5e6-96231b3b80d8
* * Set the scope attributes for the ASM symbol we added to be the value passedBill Wendling2012-03-301-14/+18
| | | | | | | | into the function. * Reorder some header files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153783 91177308-0d34-0410-b5e6-96231b3b80d8
* Rip out emission of the regIsInRegClass function for the asm printer.Benjamin Kramer2012-03-303-68/+4
| | | | | | It's slow, bloated and completely redundant with MCRegisterClass::contains. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153782 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM fix encoding fixup resolution for ldrd and friends.Jim Grosbach2012-03-301-0/+2
| | | | | | | | | The 8-bit payload is not contiguous in the opcode. Move the upper nibble over 4 bits into the correct place. rdar://11158641 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153780 91177308-0d34-0410-b5e6-96231b3b80d8
* Use SequenceToOffsetTable in emitRegisterNameString.Jakob Stoklund Olesen2012-03-302-8/+28
| | | | | | This allows suffix sharing in register names. (AX is a suffix of EAX). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153777 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply 153764 and 153761 with a fix.Jakob Stoklund Olesen2012-03-303-115/+87
| | | | | | | | | Use an explicit comparator instead of the default. The sets are sorted, but not using the default comparator. Hopefully, this will unbreak the Linux builders. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153772 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 153764 and 153761. They broke a --enable-optimized --enable-assertionsRafael Espindola2012-03-303-86/+115
| | | | | | --enable-expensive-checks build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153771 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembler should prefer non-aliases encoding of cmp.Jim Grosbach2012-03-302-6/+11
| | | | | | | | When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg, we want to use the non-negated form to make sure we prefer the normal encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153770 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM encoding for VSWP got the second operand incorrect.Jim Grosbach2012-03-302-4/+11
| | | | | | | | | Make the non-tied register operand names line up with what the base class encoding handler expects. rdar://11157236 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM can only use narrow encoding for low regs.Jim Grosbach2012-03-301-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153765 91177308-0d34-0410-b5e6-96231b3b80d8
* Compress SimpleValueType lists by sharing.Jakob Stoklund Olesen2012-03-302-22/+17
| | | | | | Many register classes have the same value types. Share the table space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153764 91177308-0d34-0410-b5e6-96231b3b80d8
* Compress register lists by sharing suffixes.Jakob Stoklund Olesen2012-03-302-93/+69
| | | | | | | | TableGen emits lists of sub-registers, super-registers, and overlaps. Put them all in a single table and use a SequenceToOffsetTable to share suffixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153761 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a SequenceToOffsetTable to TableGen.Jakob Stoklund Olesen2012-03-301-0/+123
| | | | | | | | This is similar to the StringToOffsetTable we use to produce string tables, but it can be used for other sequences than strings, and it eliminates entries for suffixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153760 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM integrated assembler should encoding choice for add/sub imm.Jim Grosbach2012-03-302-0/+33
| | | | | | | | | For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2 can be used for this syntax. Prefer the narrow encoding when possible. rdar://11156277 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153759 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle unreachable code in the dominates functions. This changes users whenRafael Espindola2012-03-306-11/+239
| | | | | | | needed for correctness, but still doesn't clean up code that now unnecessary checks for reachability. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153755 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-factored RuntimeDyLd:Danil Malyshev2012-03-309-1073/+753
| | | | | | | | | | | | | | | 1. The main works will made in the RuntimeDyLdImpl with uses the ObjectFile class. RuntimeDyLdMachO and RuntimeDyLdELF now only parses relocations and resolve it. This is allows to make improvements of the RuntimeDyLd more easily. In addition the support for COFF can be easily added. 2. Added ARM relocations to RuntimeDyLdELF. 3. Added support for stub functions for the ARM, allowing to do a long branch. 4. Added support for external functions that are not loaded from the object files, but can be loaded from external libraries. Now MCJIT can correctly execute the code containing the printf, putc, and etc. 5. The sections emitted instead functions, thanks Jim Grosbach. MemoryManager.startFunctionBody() and MemoryManager.endFunctionBody() have been removed. 6. MCJITMemoryManager.allocateDataSection() and MCJITMemoryManager. allocateCodeSection() used JMM->allocateSpace() instead of JMM->allocateCodeSection() and JMM->allocateDataSection(), because I got an error: "Cannot allocate an allocated block!" with object file contains more than one code or data sections. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153754 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing needs to be paranoid about negative immediates.Jim Grosbach2012-03-302-4/+7
| | | | | | | | Make sure to treat immediates as unsigned when doing relative comparisons. rdar://11153621 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153753 91177308-0d34-0410-b5e6-96231b3b80d8
* Add computeMaskedBitsLoad back, as it was the change to instsimplify thatRafael Espindola2012-03-301-0/+26
| | | | | | caused the slowdown last time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153747 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a note about a missed cmov -> sbb opportunity.Benjamin Kramer2012-03-301-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153741 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup whitespace. Doxygenize comments. And indent to llvm coding standards.Bill Wendling2012-03-301-214/+119
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153740 91177308-0d34-0410-b5e6-96231b3b80d8
* Ensure conditional BL instructions for ARM are given the fixup ↵James Molloy2012-03-308-12/+61
| | | | | | | | | | fixup_arm_condbranch. Patch by Tim Northover! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM target should allow codegenprep to duplicate ret instructions to enable ↵Evan Cheng2012-03-302-1/+43
| | | | | | tailcall opt. rdar://11140249 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153717 91177308-0d34-0410-b5e6-96231b3b80d8
* Testcase for r153710.Bill Wendling2012-03-301-0/+35
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153711 91177308-0d34-0410-b5e6-96231b3b80d8
* Add testcase for r153705Bill Wendling2012-03-301-0/+59
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153706 91177308-0d34-0410-b5e6-96231b3b80d8
* If we have a VLA that has a "use" in a metadata node that's then usedBill Wendling2012-03-301-1/+12
| | | | | | | | | | | | | | | | | here but it has no other uses, then we have a problem. E.g., int foo (const int *x) { char a[*x]; return 0; } If we assign 'a' a vreg and fast isel later on has to use the selection DAG isel, it will want to copy the value to the vreg. However, there are no uses, which goes counter to what selection DAG isel expects. <rdar://problem/11134152> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153705 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the constant in this testcase so that it results in a constant poolLang Hames2012-03-291-3/+3
| | | | | | | load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153704 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r153694. It was causing failures in the buildbots.Bill Wendling2012-03-2957-1828/+1073
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153701 91177308-0d34-0410-b5e6-96231b3b80d8
* Invalidate liveness in ARMConstantIslandPass.Jakob Stoklund Olesen2012-03-291-0/+4
| | | | | | | | | | This pass splits basic blocks to insert constant islands, and it doesn't recompute the live-in lists. No later passes depend on accurate liveness information. This fixes PR12410 where the machine code verifier was complaining. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153700 91177308-0d34-0410-b5e6-96231b3b80d8
* Prefer even-odd D-register pairs.Jakob Stoklund Olesen2012-03-291-1/+2
| | | | | | | | | | | We are sometimes allocatinog from the DPair register class which contains odd-even pairs in addition to the Q registers. Place the Q registers first in the DPair allocation order as they can be copied with a single instruction. The odd-even pairs should only be allocated as a last resort. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153699 91177308-0d34-0410-b5e6-96231b3b80d8
* Filecheck-ize this test so that it actually tests something reasonable.Chandler Carruth2012-03-291-2/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153697 91177308-0d34-0410-b5e6-96231b3b80d8
* Try using vmov.i32 to materialize FP32 constants that can't be materialized byLang Hames2012-03-291-23/+54
| | | | | | | vmov.f32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153696 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-factored RuntimeDyld.Danil Malyshev2012-03-2957-1073/+1828
| | | | | | Added ExecutionEngine/MCJIT tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153694 91177308-0d34-0410-b5e6-96231b3b80d8
* Lowercase the tag name to match the rest of dwarf.Eric Christopher2012-03-294-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153691 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly 'cmp lr, #0' should not encode using 'cmn'.Jim Grosbach2012-03-294-4/+10
| | | | | | | | | The CMP->CMN alias was matching for an immediate of zero when it should only match for negative values. rdar://11129224 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153689 91177308-0d34-0410-b5e6-96231b3b80d8
* The shuffle scheduler is only available in asserts build - make misched-new.llLang Hames2012-03-291-0/+1
| | | | | | | testcase require asserts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153687 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle register copies for the new ARM register classes.Jakob Stoklund Olesen2012-03-291-19/+41
| | | | | | | | | | | | | ARM recently gained DPair, DTriple, and DQuad register classes. Update copyPhysReg() to handle copies in these register classes. No test case, it is difficult to make the register allocator emit the odd copies reliably. The missing DPair copy caused a failure on partialsums in the nightly test suite. <rdar://problem/11147997> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153686 91177308-0d34-0410-b5e6-96231b3b80d8
* Drop O4 from the llc manpage, it was removed in r70445.Benjamin Kramer2012-03-291-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153684 91177308-0d34-0410-b5e6-96231b3b80d8
* Make x86 REP_MOV* and REP_STO instructions use the correct operand sizes in ↵Lang Hames2012-03-292-25/+59
| | | | | | 64-bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153680 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix missed files in JIT unittests MakefileDanil Malyshev2012-03-291-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153672 91177308-0d34-0410-b5e6-96231b3b80d8
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