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* Rename PathV2 to just Path now that it is the only one.Rafael Espindola2013-06-264-11/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185015 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Do not emit ".option pic0" if target is mips64.Akira Hatanaka2013-06-262-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185012 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Improve code generation for constant multiplication using shifts, ↵Akira Hatanaka2013-06-262-0/+103
| | | | | | | | | | adds and subs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185011 91177308-0d34-0410-b5e6-96231b3b80d8
* [APFloat] Removed debugging cruft that snuck in.Michael Gottesman2013-06-261-4/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184974 91177308-0d34-0410-b5e6-96231b3b80d8
* The SLP Vectorizer works across basic blocks. Update the docs.Nadav Rotem2013-06-261-9/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184973 91177308-0d34-0410-b5e6-96231b3b80d8
* Use enums instead of raw octal values.Rafael Espindola2013-06-263-4/+8
| | | | | | Patch by 罗勇刚(Yonggang Luo). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184971 91177308-0d34-0410-b5e6-96231b3b80d8
* Erase all of the instructions that we RAUWedNadav Rotem2013-06-262-1/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184969 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a subtarget feature 'v8' to the ARM backend.Joey Gouly2013-06-269-11/+41
| | | | | | | This allows for targeting the ARMv8 AArch32 variant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184967 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not add cse-ed instructions into the visited map because we dont want to ↵Nadav Rotem2013-06-262-5/+93
| | | | | | consider them as a candidate for replacement of instructions to be visited. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184966 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix more cases where predication may or may not be allowedTim Northover2013-06-268-36/+100
| | | | | | | | | | Unfortunately this addresses two issues (by the time I'd disentangled the logic it wasn't worth putting it back to half-broken): + Coprocessor instructions should all be predicable in Thumb mode. + BKPT should never be predicable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184965 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: allow predicated barriers in Thumb modeTim Northover2013-06-265-28/+61
| | | | | | | The barrier instructions are only "always-execute" in ARM mode, they can quite happily sit inside an IT block in Thumb. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184964 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the 'generic' CPU from the ARM eabi attributes printer.Joey Gouly2013-06-262-13/+5
| | | | | | | Make v4 the default ARM architecture attribute, to match CodeGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184962 91177308-0d34-0410-b5e6-96231b3b80d8
* PathV1 is deprecated since the 18th of Dec 2010. Remove it.Rafael Espindola2013-06-265-1571/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184960 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a convenience functions that don't return if the directory existed.Rafael Espindola2013-06-261-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184955 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused includes.Rafael Espindola2013-06-263-3/+0
| | | | | | llvm itself is now PathV1 clean. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184947 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Accept 17-bit signed immediates for addisUlrich Weigand2013-06-265-4/+42
| | | | | | | | | | | | | | | | | | | | | The assembler currently strictly verifies that immediates for s16imm operands are in range (-32768 ... 32767). This matches the behaviour of the GNU assembler, with one exception: gas allows, as a special case, operands in an extended range (-65536 .. 65535) for the addis instruction only (and its extended mnemonic lis). The main reason for this seems to be to allow using unsigned 16-bit operands for lis, e.g. like lis %r1, 0xfedc. Since this has been supported by gas for a long time, and assembler source code seen "in the wild" actually exploits this feature, this patch adds equivalent support to LLVM for compatibility reasons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184946 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support symbolic u16imm operandsUlrich Weigand2013-06-266-9/+24
| | | | | | | | | | | | | | | | Currently, all instructions taking s16imm operands support symbolic operands. However, for u16imm operands, we only support actual immediate integers. This causes the assembler to reject code like ori %r5, %r5, symbol@l This patch changes the u16imm operand definition to likewise accept symbolic operands. In fact, s16imm and u16imm can share the same encoding routine, now renamed to getImm16Encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184944 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: operands should be explicit when disassembledAmaury de la Vieuville2013-06-262-8/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184943 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc]: Add memory operands for the frame references in the storeRegToStackSlotVenkatraman Govindaraju2013-06-261-8/+30
| | | | | | | and loadRegFromStackSlot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184935 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a comment.Elena Demikhovsky2013-06-261-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184933 91177308-0d34-0410-b5e6-96231b3b80d8
* Suppress llvm/test/Other/can-execute.txt on msys bash.NAKAMURA Takumi2013-06-262-1/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184932 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimized integer vector multiplication operation by replacing it with ↵Elena Demikhovsky2013-06-267-25/+148
| | | | | | shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184931 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] workaround for PR16277: don't instrument AllocaInstr with alignment ↵Kostya Serebryany2013-06-262-1/+21
| | | | | | more than the redzone size git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184928 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] add option -asan-keep-uninstrumented-functionsKostya Serebryany2013-06-262-4/+70
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184927 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide bootstrap support to build only llvm+clang when using cmake.Andy Gibbs2013-06-261-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Where a source tree is complete with lld, lldb and polly, it may not be possible to use cmake to configure build scripts if the host compiler it not capable of compiling these sub-projects. This change makes it possible to first build a bootstrap clang compiler when can then be used to build a complete llvm toolchain. An example bootstrap build sequence could be as follows: $ mkdir bootstrap $ cd bootstrap $ cmake -G 'Unix Makefiles' -DCMAKE_BUILD_TYPE:STRING=Release -DCMAKE_PREFIX_PATH:STRING=$(pwd) -DLLVM_TARGETS_TO_BUILD:STRING=host -DLLVM_INCLUDE_TOOLS:STRING=bootstrap-only ../source $ make clang # build clang only for host $ cd .. $ export CC=$(realpath bootstrap/bin)/clang $ export CXX=$(realpath bootstrap/bin)/clang++ $ mkdir final $ cd final $ cmake -G 'Unix Makefiles' ../source $ make all check-all git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184924 91177308-0d34-0410-b5e6-96231b3b80d8
* Support using "host" as a target in LLVM_TARGETS_TO_BUILD when using cmake.Andy Gibbs2013-06-262-12/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184923 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove calls to Path in #ifdefs that don't seem to be used in any of the ↵Rafael Espindola2013-06-261-3/+3
| | | | | | bots :-( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184920 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a simpler version of remove_all.Rafael Espindola2013-06-261-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184919 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the build when __APPLE__ is defined.Rafael Espindola2013-06-261-1/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184917 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove sys::GetMainExecutable.Rafael Espindola2013-06-263-121/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184916 91177308-0d34-0410-b5e6-96231b3b80d8
* Port GetMainExecutable over to PathV2.Rafael Espindola2013-06-266-8/+126
| | | | | | I will remove the V1 version as soon as I change clang in the next commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184914 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove PathWithStatus.Rafael Espindola2013-06-263-135/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184910 91177308-0d34-0410-b5e6-96231b3b80d8
* dbgs() << Instruction doesn't print a newline on the end any more. Update theseNick Lewycky2013-06-261-5/+5
| | | | | | | | debug statements to add a missing newline. Also canonicalize to '\n' instead of "\n"; the latter calls a function with a loop the former does not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184897 91177308-0d34-0410-b5e6-96231b3b80d8
* s/C++0x/C++11/Adrian Prantl2013-06-251-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184892 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge isReachable into isBackedge.Jakob Stoklund Olesen2013-06-251-19/+10
| | | | | | Prefer using RPO.lookup() instead of RPO[] which can mutate the map. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184891 91177308-0d34-0410-b5e6-96231b3b80d8
* SLPVectorizer: support slp-vectorization of PHINodes between basic blocksNadav Rotem2013-06-252-1/+142
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184888 91177308-0d34-0410-b5e6-96231b3b80d8
* Print block frequencies in decimal form.Jakob Stoklund Olesen2013-06-252-17/+26
| | | | | | | | | This is easier to read than the internal fixed-point representation. If anybody knows the correct algorithm for converting fixed-point numbers to base 10, feel free to fix it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184881 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use new getNamedOperandIdx function generated by TableGenTom Stellard2013-06-2511-228/+219
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184880 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Generate a function for getting operand indices based on their ↵Tom Stellard2013-06-253-0/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | defined names This patch modifies TableGen to generate a function in ${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used to look up indices for operands based on their names. In order to activate this feature for an instruction, you must set the UseNamedOperandTable bit. For example, if you have an instruction like: def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>; You can look up the operand indices using the new function, like this: Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0 Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1 Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2 The operand names are case sensitive, so $dst and $DST are considered different operands. This change is useful for R600 which has instructions with a large number of operands, many of which model single bit instruction configuration values. These configuration bits are common across most instructions, but may have a different operand index depending on the instruction type. It is useful to have a convenient way to look up the operand indices, so these bits can be generically set on any instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184879 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 cost model: Vectorizing integer division is a bad ideaArnold Schwaighofer2013-06-252-0/+57
| | | | | | radar://14057959 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184872 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix SROA to avoid unnecessary scalar conversions for 1-element vectors.Bob Wilson2013-06-252-15/+40
| | | | | | | | | | | When a 1-element vector alloca is promoted, a store instruction can often be rewritten without converting the value to a scalar and using an insertelement instruction to stuff it into the new alloca. This patch just adds a check to skip that conversion when it is unnecessary. This turns out to be really important for some ARM Neon operations where <1 x i64> is used to get around the fact that i64 is not a legal type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184870 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused code. No functionality change.Manman Ren2013-06-251-4/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184866 91177308-0d34-0410-b5e6-96231b3b80d8
* The GCDA 402 format won't have a second checksum either.Bill Wendling2013-06-251-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184864 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support @got modifierUlrich Weigand2013-06-256-0/+85
| | | | | | | | | Add VK_... values and relocation types necessary to support the @got family of modifiers. Used by the asm parser only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184860 91177308-0d34-0410-b5e6-96231b3b80d8
* Move GetEXESuffix to the one place it is used.Rafael Espindola2013-06-254-15/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184853 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove sys::PathSeparator.Rafael Espindola2013-06-253-8/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184852 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Consolidate expansion of v2i32/v4i32 ops for EG/SIAaron Watry2013-06-253-49/+22
| | | | | | | | | | | By default, we expand these operations for both EG and SI. Move the duplicated code into a common space for now. If the targets ever actually implement these operations as instructions, we can override that in the relevant target. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184848 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add v2i32 test for vselectAaron Watry2013-06-251-6/+20
| | | | | | | | | | | | | | Note: Only adding test for evergreen, not SI yet. When I attempted to expand vselect for SI, I got the following: llc: /home/awatry/src/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:522: llvm::SDValue llvm::DAGTypeLegalizer::PromoteIntRes_SETCC(llvm::SDNode*): Assertion `SVT.isVector() == N->getOperand(0).getValueType().isVector() && "Vector compare must return a vector result!"' failed. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184847 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Expand xor v2i32/v4i32Aaron Watry2013-06-252-7/+36
| | | | | | | | Add test cases for both vector sizes on SI and also add v2i32 test for EG. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184846 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add v2i32 test for setcc on evergreenAaron Watry2013-06-251-3/+22
| | | | | | | | | | | No test/expansion for SI has been added yet. Attempts to expand this operation for SI resulted in a stacktrace in (IIRC) LegalizeIntegerTypes which was complaining about vector comparisons being required to return a vector type. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184845 91177308-0d34-0410-b5e6-96231b3b80d8
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