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* Fix MemoryBuffer breakage correctly.Jeff Cohen2007-04-294-1626/+1411
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* Unbreak VC++ build.Jeff Cohen2007-04-292-6/+9
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* Unbreak build.Jeff Cohen2007-04-291-1/+2
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* Updated aliases testAnton Korobeynikov2007-04-291-2/+4
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* Implement support to read an arbitrary bitcode file. Next up, dumping theChris Lattner2007-04-291-9/+78
| | | | | | | file symbolically and actually computing statistics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36557 91177308-0d34-0410-b5e6-96231b3b80d8
* very early support for analyzing a bitstream. This opens the file, startsChris Lattner2007-04-291-7/+67
| | | | | | | reading the stream, and detects whether it is LLVM IR or not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36556 91177308-0d34-0410-b5e6-96231b3b80d8
* make this file self-containedChris Lattner2007-04-291-0/+1
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* Switch the bitcode reader interface to take a MemoryBuffer instead of knowingChris Lattner2007-04-295-119/+96
| | | | | | | | | | | | | | | anything about disk I/O itself. This greatly simplifies its interface - eliminating the need for the ReaderWrappers.cpp file. This adds a new option to llvm-dis (-bitcode) which instructs it to read the input file as bitcode. Until/unless the bytecode reader is taught to read from MemoryBuffer, there is no way to handle stdin reading without it. I don't plan to switch the bytecode reader over, I'd rather delete it :), so the option will stay around temporarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36554 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new memorybuffer class, to unify all the file reading code in the systemChris Lattner2007-04-292-0/+322
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* new method for creating a path, which does not create a temporary string.Chris Lattner2007-04-291-0/+8
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* fit in 80 colsChris Lattner2007-04-291-6/+5
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* Fix this to use the right block IDChris Lattner2007-04-291-3/+1
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* moved Writer.cpp -> BitcodeWriter.cpp to make it more unique in the tree.Chris Lattner2007-04-291-1/+1
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* Minor corrections.Jeff Cohen2007-04-291-61/+60
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* memory operands that have a direct operand should have their stores createdChris Lattner2007-04-281-35/+42
| | | | | | | | | | | | | | before the copies into physregs are done. This avoids having flag operands skip the store, causing cycles in the dag at sched time. This fixes infinite loops on these tests: test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll for PR1308 test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll for PR828 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36547 91177308-0d34-0410-b5e6-96231b3b80d8
* eliminate more redundant constraint type analysisChris Lattner2007-04-281-6/+2
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* merge constraint type analysis stuff together.Chris Lattner2007-04-281-14/+21
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* Significant refactoring of the inline asm stuff, to support future changes.Chris Lattner2007-04-281-82/+107
| | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36544 91177308-0d34-0410-b5e6-96231b3b80d8
* Regenerate.Reid Spencer2007-04-284-2365/+2021
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* Revert the premature portion of the last commit.Reid Spencer2007-04-281-62/+76
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* This is not "FIXME" anymoreAnton Korobeynikov2007-04-281-3/+1
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* Let Verifier check aliaseesAnton Korobeynikov2007-04-281-0/+7
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* Fix a compilation error (jump to case label).Reid Spencer2007-04-281-77/+64
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* RegenerateAnton Korobeynikov2007-04-283-3352/+4719
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* Implement review feedback. Aliasees can be either GlobalValue's orAnton Korobeynikov2007-04-2820-113/+231
| | | | | | | bitcasts of them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36537 91177308-0d34-0410-b5e6-96231b3b80d8
* memory inputs to an inline asm are required to have an address available.Chris Lattner2007-04-282-20/+34
| | | | | | | | | | If the operand is not already an indirect operand, spill it to a constant pool entry or a stack slot. This fixes PR1356 and CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36536 91177308-0d34-0410-b5e6-96231b3b80d8
* new testcase for PR1356Chris Lattner2007-04-281-0/+12
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* Fix CodeGen/Generic/2007-04-27-LargeMemObject.ll andChris Lattner2007-04-281-4/+10
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* ensure the operand prints.Chris Lattner2007-04-281-1/+1
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* new testcaseChris Lattner2007-04-282-0/+21
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* update syntaxChris Lattner2007-04-284-5/+5
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* not fully implemented yet.Chris Lattner2007-04-281-0/+2
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* add a default parameterChris Lattner2007-04-281-3/+5
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* add a way to make this less brittleChris Lattner2007-04-282-5/+10
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* fix a bug triggered by 403.gccChris Lattner2007-04-281-2/+1
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* update for new inline asm syntaxChris Lattner2007-04-282-3/+3
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* Fix several latent bugs in EmitGEPOffset that didn't manifest with itsChris Lattner2007-04-281-36/+52
| | | | | | | previous clients. This fixes MallocBench/gs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36525 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix this to match change to InlineAsm class.Chris Lattner2007-04-281-3/+3
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* uhn zap cvsChris Lattner2007-04-281-6/+0
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* represent indirect operands explicitly in inline asm strings.Chris Lattner2007-04-282-13/+16
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* Implement PR1345 and Transforms/InstCombine/bitcast-gep.llChris Lattner2007-04-281-28/+104
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* new testcaseChris Lattner2007-04-281-0/+19
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* change per reviewDale Johannesen2007-04-281-3/+3
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* Prevent Thumb code from generating ARM instructionsDale Johannesen2007-04-271-3/+3
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* fix the test tls1.Lauro Ramos Venancio2007-04-271-6/+7
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* add TLS tests.Lauro Ramos Venancio2007-04-272-0/+38
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* add a GEP helper functionChris Lattner2007-04-272-0/+17
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* add parenthesis.Lauro Ramos Venancio2007-04-271-2/+2
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* Doh. ARM::LEApcrel is a single instruction MI.Evan Cheng2007-04-271-5/+3
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* In Thumb mode, the frame register must be R7.Lauro Ramos Venancio2007-04-272-2/+11
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