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* Clean up ConstantRange a bit:Nick Lewycky2010-08-113-98/+127
| | | | | | | | | | - remove ashr which never worked. - fix lshr and shl and add tests. - remove dead function "intersect1Wrapped". - add a new sub method to subtract ranges, with test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110861 91177308-0d34-0410-b5e6-96231b3b80d8
* Add testcases for all AVX 256-bit intrinsics added in the last couple daysBruno Cardoso Lopes2010-08-111-0/+751
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110854 91177308-0d34-0410-b5e6-96231b3b80d8
* Make LoopPass::getContainedPass return a LoopPass* instead of a Pass*Dan Gohman2010-08-112-8/+8
| | | | | | | and remove casts from all its callers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110848 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove BasicBlockPass::runOnFunction, which was unused.Dan Gohman2010-08-112-16/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110847 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove rsqrt/sqrt_nr intrinsics since there are no more builtins for them on ↵Bruno Cardoso Lopes2010-08-111-5/+0
| | | | | | clang git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110845 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete FunctionPass::run, which is unused.Dan Gohman2010-08-112-16/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110843 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete FunctionPass::runOnModule, which is unused.Dan Gohman2010-08-112-19/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110842 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use unsigned char for alignments in TargetData. There aren'tDan Gohman2010-08-112-34/+34
| | | | | | | | | that many of these things, so the memory savings isn't significant, and there are now situations where there can be alignments greater than 128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110836 91177308-0d34-0410-b5e6-96231b3b80d8
* Use ISD::ADD instead of ISD::SUB with a negated constant. ThisDan Gohman2010-08-111-4/+5
| | | | | | | | | | | | avoids trouble if the return type of TD->getPointerSize() is changed to something which doesn't promote to a signed type, and is simpler anyway. Also, use getCopyFromReg instead of getRegister to read a physical register's value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110835 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r109881 using a more strict command line for llc.Bruno Cardoso Lopes2010-08-112-0/+2006
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110833 91177308-0d34-0410-b5e6-96231b3b80d8
* fix silly typoJim Grosbach2010-08-111-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110831 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a target triple, as the runtime library invocation varies a bit byJim Grosbach2010-08-111-3/+3
| | | | | | | | | | | platform. It's apparently "bl __muldf3" on linux, for example. Since that's not what we're checking here, it's more robust to just force a triple. We just wwant to check that the inline FP instructions are only generated on cpus that have them." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110830 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test and re-enable it.Evan Cheng2010-08-111-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110829 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a FIXME. The SlotIndex::Slot enum should be private.Jakob Stoklund Olesen2010-08-112-16/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110826 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily disable some failing tests, until they can beDan Gohman2010-08-111-2/+2
| | | | | | | properly investigated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110825 91177308-0d34-0410-b5e6-96231b3b80d8
* cortex m4 has floating point support, but only single precision.Jim Grosbach2010-08-115-2/+35
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110810 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily disable some failing tests, until they can beDan Gohman2010-08-111-2/+2
| | | | | | | properly investigated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110808 91177308-0d34-0410-b5e6-96231b3b80d8
* Consider this code snippet:Bill Wendling2010-08-113-3/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | float t1(int argc) { return (argc == 1123) ? 1.234f : 2.38213f; } We would generate truly awful code on ARM (those with a weak stomach should look away): _t1: movw r1, #1123 movs r2, #1 movs r3, #0 cmp r0, r1 mov.w r0, #0 it eq moveq r0, r2 movs r1, #4 cmp r0, #0 it ne movne r3, r1 adr r0, #LCPI1_0 ldr r0, [r0, r3] bx lr The problem was that legalization was creating a cascade of SELECT_CC nodes, for for the comparison of "argc == 1123" which was fed into a SELECT node for the ?: statement which was itself converted to a SELECT_CC node. This is because the ARM back-end doesn't have custom lowering for SELECT nodes, so it used the default "Expand". I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this testcase, but can obviously be expanded to include more cases. Now we generate this, which looks optimal to me: _t1: movw r1, #1123 movs r2, #0 cmp r0, r1 adr r0, #LCPI0_0 it eq moveq r2, #4 ldr r0, [r0, r2] bx lr .align 2 LCPI0_0: .long 1075344593 @ float 2.382130e+00 .long 1067316150 @ float 1.234000e+00 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110799 91177308-0d34-0410-b5e6-96231b3b80d8
* Report error if codegen tries to instantiate a ARM target when the cpu does ↵Evan Cheng2010-08-116-13/+15
| | | | | | support it. e.g. cortex-m* processors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798 91177308-0d34-0410-b5e6-96231b3b80d8
* ArchV7M implies HW division instructions.Evan Cheng2010-08-111-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110797 91177308-0d34-0410-b5e6-96231b3b80d8
* ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON.Evan Cheng2010-08-111-11/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110796 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)Evan Cheng2010-08-113-38/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/ARM: Add basic support for handling predication by parsing it out of the ↵Daniel Dunbar2010-08-112-1/+52
| | | | | | mnemonic into a separate operand form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110794 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/ARM: Split mnemonic on '.' characters.Daniel Dunbar2010-08-111-3/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110793 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/ARM: Fill in ARMOperand::dump a bit.Daniel Dunbar2010-08-111-1/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110792 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-mc: Add -show-inst-operands, for dumping the parsed instruction ↵Daniel Dunbar2010-08-114-1/+26
| | | | | | representation before matching. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110791 91177308-0d34-0410-b5e6-96231b3b80d8
* MCAsmParser: Add dump() hook to MCParsedAsmOperand.Daniel Dunbar2010-08-114-6/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110790 91177308-0d34-0410-b5e6-96231b3b80d8
* tblgen/AsmMatcher: Treat '.' in assembly strings as a token separator.Daniel Dunbar2010-08-111-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110789 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/ARM: Add an ARMOperand class for condition codes.Daniel Dunbar2010-08-112-4/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110788 91177308-0d34-0410-b5e6-96231b3b80d8
* Really control isel of barrier instructions with cpu feature.Evan Cheng2010-08-112-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110787 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bitEvan Cheng2010-08-112-5/+17
| | | | | | | instructions: dmb, dsb, isb, msr, and mrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110786 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add subtarget feature -mattr=+db which determine whether an ARM cpu has theEvan Cheng2010-08-119-55/+88
| | | | | | | | | | memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/ARM: Switch to using the generated match functions instead of stub ↵Daniel Dunbar2010-08-111-81/+30
| | | | | | implementations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110783 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/ARM: Enable generation of the ARM asm matcher, not that it can do much.Daniel Dunbar2010-08-112-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110782 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Mark some disassembler only instructions as not available for matching --Daniel Dunbar2010-08-111-0/+4
| | | | | | | for some reason they have a very odd MCInst form where the operands overlap, but I haven't dug in to find out why yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110781 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Quote $p in an asm string.Daniel Dunbar2010-08-111-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110780 91177308-0d34-0410-b5e6-96231b3b80d8
* tblgen/AsmMatcher: Downgrade instructions with tied operands to a debug-only ↵Daniel Dunbar2010-08-111-3/+6
| | | | | | warning, for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110779 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve indentation.Owen Anderson2010-08-111-27/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110778 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove AVX 256-bit cast intrinsics now that clang is using ↵Bruno Cardoso Lopes2010-08-111-12/+0
| | | | | | __builtin_shufflevector for those git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110772 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove AVX 256-bit unpack and interleave intrinsics now that clang is using ↵Bruno Cardoso Lopes2010-08-111-16/+0
| | | | | | __builtin_shufflevector for those git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110769 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove AVX 256-bit shuffle intrinsics now that clang is using ↵Bruno Cardoso Lopes2010-08-111-10/+0
| | | | | | __builtin_shufflevector for those git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110767 91177308-0d34-0410-b5e6-96231b3b80d8
* Update test to match output of optimize compares for ARM.Bill Wendling2010-08-111-4/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110765 91177308-0d34-0410-b5e6-96231b3b80d8
* CMake: corrections on LLVM.cmake external services.Oscar Fuentes2010-08-113-4/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110763 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds.Bill Wendling2010-08-111-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110762 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark ARM compare instructions as isCompare.Bill Wendling2010-08-111-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110761 91177308-0d34-0410-b5e6-96231b3b80d8
* Make it possible to set the cpu used for codegen.Rafael Espindola2010-08-115-1/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110759 91177308-0d34-0410-b5e6-96231b3b80d8
* When analyzing loop exit conditions combined with and and or, don'tDan Gohman2010-08-112-16/+52
| | | | | | | | make any assumptions about when the two conditions will agree on when to permit the loop to exit. This fixes PR7845. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110758 91177308-0d34-0410-b5e6-96231b3b80d8
* lto: Fix an inverted conditional which prevented the addition of symbols scrapedDaniel Dunbar2010-08-111-1/+1
| | | | | | | | from inline assembly, except in cases where they had already been seen (in which case they would get added twice). - I can't see how this ever worked... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110757 91177308-0d34-0410-b5e6-96231b3b80d8
* lto: Fix gratuitous memory leaks.Daniel Dunbar2010-08-111-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110756 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a separate ARM instruction format for Saturate instructions.Bob Wilson2010-08-117-181/+208
| | | | | | | | | | (I discovered 2 more copies of the ARM instruction format list, bringing the total to 4!! Two of them were already out of sync. I haven't yet gotten into the disassembler enough to know the best way to fix this, but something needs to be done.) Add support for encoding these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110754 91177308-0d34-0410-b5e6-96231b3b80d8
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