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* Reapply commit 158073 with a fix (the testcase was already committed). TheDuncan Sands2012-06-081-123/+120
| | | | | | | | | | | | | | | | | | | problem was that by moving instructions around inside the function, the pass could accidentally move the iterator being used to advance over the function too. Fix this by only processing the instruction equal to the iterator, and leaving processing of instructions that might not be equal to the iterator to later (later = after traversing the basic block; it could also wait until after traversing the entire function, but this might make the sets quite big). Original commit message: Grab-bag of reassociate tweaks. Unify handling of dead instructions and instructions to reoptimize. Exploit this to more systematically eliminate dead instructions (this isn't very useful in practice but is convenient for analysing some testcase I am working on). No need for WeakVH any more: use an AssertingVH instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158226 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the TODO statement in the PPC README re: CTR loopsHal Finkel2012-06-081-1/+0
| | | | | | | | As Chris points out, this can now be removed! TODO: check if the associated section on viterbi's inner loop can also be removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158224 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable PPC CTR loop formation by default.Hal Finkel2012-06-084-13/+11
| | | | | | | | | | | | | | | | | | | | | | Thanks to Jakob's help, this now causes no new test suite failures! Over the entire test suite, this gives an average 1% speedup. The largest speedups are: SingleSource/Benchmarks/Misc/pi - 108% SingleSource/Benchmarks/CoyoteBench/lpbench - 54% MultiSource/Benchmarks/Prolangs-C/unix-smail/unix-smail - 50% SingleSource/Benchmarks/Shootout/ary3 - 32% SingleSource/Benchmarks/Shootout-C++/matrix - 30% The largest slowdowns are: MultiSource/Benchmarks/mediabench/gsm/toast/toast - -30% MultiSource/Benchmarks/Prolangs-C/bison/mybison - -25% MultiSource/Benchmarks/BitBench/uuencode/uuencode - -22% MultiSource/Applications/d/make_dparser - -14% SingleSource/Benchmarks/Shootout-C++/ary - -13% In light of these slowdowns, additional profiling work is obviously needed! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158223 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark the PPC CTRRC and CTRRC8 register classes as non-allocatable.Hal Finkel2012-06-081-2/+10
| | | | | | | | | | | Marking these classes as non-alocatable allows CTR loop generation to work correctly with the block placement passes, etc. These register classes are currently used only by some unused TCRETURN patterns. In future cleanup, these will be removed. Thanks again to Jakob for suggesting this fix to the CTR loop problem! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158221 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable optimization for integer ABS on X86 if Subtarget has CMOV.Manman Ren2012-06-081-3/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158220 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r158160Manman Ren2012-06-081-0/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158218 91177308-0d34-0410-b5e6-96231b3b80d8
* Sched itinerary fix: Avoid static initializers.Andrew Trick2012-06-082-5/+14
| | | | | | | | This fixes an accidental dependence on static initialization order that I introduced yesterday. Thank you Lang!!! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158215 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a crash in APInt::lshr when shiftAmt > BitWidth.Chad Rosier2012-06-082-1/+9
| | | | | | | Patch by James Benton <jbenton@vmware.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158213 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Target->Codegen dependence.Andrew Trick2012-06-082-195/+205
| | | | | | | | | | | | | | | | | Bulk move of TargetInstrInfo implementation into TargetInstrInfoImpl. This is dirty because the code isn't part of TargetInstrInfoImpl class, nor should it be, because the methods are not target hooks. However, it's the current mechanism for keeping libTarget useful outside the backend. You'll get a not-so-nice link error if you invoke a TargetInstrInfo method that depends on CodeGen. The TargetInstrInfoImpl class should probably be removed since it doesn't really solve this problem. To really fix this, we probably need separate interfaces for the CodeGen/nonCodeGen sides of TargetInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158212 91177308-0d34-0410-b5e6-96231b3b80d8
* BoundsChecking: add support for ConstantPointerNull. fixes a bunch of ↵Nuno Lopes2012-06-081-6/+7
| | | | | | instrumentation failures in loops with reallocs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158210 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/Generic/APIntLoadStore.ll: Mark as XFAIL:ppc since r157911.NAKAMURA Takumi2012-06-081-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158209 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable the PPC CTR-Loops pass by default.Hal Finkel2012-06-084-6/+19
| | | | | | | | | | The pass itself works well, but the something in the Machine* infrastructure does not understand terminators which define registers. Without the ability to use the block-placement pass, etc. this causes performance regressions (and so is turned off by default). Turning off the analysis turns off the problems with the Machine* infrastructure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158206 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in the new PPC CTR-Loops pass.Hal Finkel2012-06-082-0/+88
| | | | | | | | | The code which tests for an induction operation cannot assume that any ADDI instruction will have a register operand because the operand could also be a frame index; for example: %vreg16<def> = ADDI8 <fi#0>, 0; G8RC:%vreg16 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158205 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form ↵Hal Finkel2012-06-0810-18/+890
| | | | | | | | | | CTR-based loop branching code. This pass is derived from the Hexagon HardwareLoops pass. The only significant enhancement over the Hexagon pass is that PPCCTRLoops will also attempt to delete the replaced add and compare operations if they are no longer otherwise used. Also, invalid preheader DebugLoc is not used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158204 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert commit 158073 while waiting for a fix. The issue is that reassociateDuncan Sands2012-06-082-111/+144
| | | | | | | | | | | | | | | | | | can move instructions within the instruction list. If the instruction just happens to be the one the basic block iterator is pointing to, and it is moved to a different basic block, then we get into an infinite loop due to the iterator running off the end of the basic block (for some reason this doesn't fire any assertions). Original commit message: Grab-bag of reassociate tweaks. Unify handling of dead instructions and instructions to reoptimize. Exploit this to more systematically eliminate dead instructions (this isn't very useful in practice but is convenient for analysing some testcase I am working on). No need for WeakVH any more: use an AssertingVH instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158199 91177308-0d34-0410-b5e6-96231b3b80d8
* cmake: Pass the -m32 flag to modules if LLVM_BUILD_32_BITS is enabledTobias Grosser2012-06-081-0/+1
| | | | | | | | | | | This was previously only done for executables and shared libraries, but not for modules. As modules are essentially shared libraries (that need to be dlopened explicitly), threating them the same as shared libraries seems reasonable. This fixes the LLVM_BUILD_32_BITS build of Polly. Contributed by: Ondra Hosek <ondra.hosek@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158195 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the AsmMatcherEmitter to allow InstAlias' where the suboperands of a ↵Owen Anderson2012-06-082-5/+27
| | | | | | complex operand are called out explicitly in the asm string. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158183 91177308-0d34-0410-b5e6-96231b3b80d8
* [CMake] Promote extension warnings to errors.Michael J. Spencer2012-06-071-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158176 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: optimize generated code for integer ABSManman Ren2012-06-072-8/+54
| | | | | | | | | | | | | | | | | | | | | This patch will generate the following for integer ABS: movl %edi, %eax negl %eax cmovll %edi, %eax INSTEAD OF movl %edi, %ecx sarl $31, %ecx leal (%rdi,%rcx), %eax xorl %ecx, %eax There exists a target-independent DAG combine for integer ABS, which converts integer ABS to sar+add+xor. For X86, we match this pattern back to neg+cmov. This is implemented in PerformXorCombine. rdar://10695237 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158175 91177308-0d34-0410-b5e6-96231b3b80d8
* [CMake] Order MSVC warnings numerically.Michael J. Spencer2012-06-071-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158171 91177308-0d34-0410-b5e6-96231b3b80d8
* [CMake] Adjust MSVC warnings.Michael J. Spencer2012-06-071-2/+6
| | | | | | | Remove /Wall from LLVM_ENABLE_WARNINGS (it's useless) and promote 4239 to a level 1 warning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158170 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not optimize the used bits of the x86 vselect condition operand, when the ↵Nadav Rotem2012-06-071-4/+6
| | | | | | | | | | condition operand is a vector of 1-bit predicates. This may happen on MIC devices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158168 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in FoldSelectOpOp. Bitcast ops may change the number of vector ↵Nadav Rotem2012-06-072-0/+17
| | | | | | elements, which may disagree with the select condition type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158166 91177308-0d34-0410-b5e6-96231b3b80d8
* Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.Andrew Trick2012-06-073-24/+76
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158164 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM getOperandLatency rewrite.Andrew Trick2012-06-071-85/+112
| | | | | | Match expectations of the new latency API. Cleanup and make the logic consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158163 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM getOperandLatency should return -1 for unknown, consistent with APIAndrew Trick2012-06-071-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158162 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM getInstrLatency logic to work with the current API.Andrew Trick2012-06-071-13/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158161 91177308-0d34-0410-b5e6-96231b3b80d8
* PR13046: we can't replace usage of SUB with CMP in the lowering phase.Manman Ren2012-06-071-1/+2
| | | | | | | It will cause assertion failure later on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158160 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a base register instead of an index register with the local dynamic model.Rafael Espindola2012-06-072-1/+9
| | | | | | Fixes pr13048. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158158 91177308-0d34-0410-b5e6-96231b3b80d8
* Move terminator machine verification to check ↵Pete Cooper2012-06-071-11/+11
| | | | | | MachineBasicBlock::instr_iterator instead of MBB::iterator git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158154 91177308-0d34-0410-b5e6-96231b3b80d8
* Add internal read flags to MachineInstrBuilder and hook them into the ↵Pete Cooper2012-06-072-3/+9
| | | | | | MachineOperand flag of the same name git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158137 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding a missing -S to the opt invocation.Meador Inge2012-06-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158128 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: replace SUB with CMP if possibleManman Ren2012-06-072-1/+25
| | | | | | | | | | | | | | | | | | | This patch will optimize the following movq %rdi, %rax subq %rsi, %rax cmovsq %rsi, %rdi movq %rdi, %rax to cmpq %rsi, %rdi cmovsq %rsi, %rdi movq %rdi, %rax Perform this optimization if the actual result of SUB is not used. rdar: 11540023 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158126 91177308-0d34-0410-b5e6-96231b3b80d8
* Spell optimization name correclty.Bill Wendling2012-06-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158123 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r157755.Manman Ren2012-06-065-61/+0
| | | | | | | | | The commit is intended to fix rdar://11540023. It is implemented as part of peephole optimization. We can actually implement this in the SelectionDAG lowering phase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158122 91177308-0d34-0410-b5e6-96231b3b80d8
* Another testcase for r156548.Bill Wendling2012-06-061-0/+162
| | | | | | | <rdar://problem/10889741> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158121 91177308-0d34-0410-b5e6-96231b3b80d8
* [llvm-nm] Update documentation to cover object file support and arguments.Michael J. Spencer2012-06-062-38/+73
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158120 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly verify liveness with bundled machine instructions.Jakob Stoklund Olesen2012-06-061-13/+34
| | | | | | | | Bundles should be treated as one atomic transaction when checking liveness. That is how the register allocator (and VLIW targets) treats bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158116 91177308-0d34-0410-b5e6-96231b3b80d8
* Add accessors for all private members of DisasmContext.Benjamin Kramer2012-06-061-0/+8
| | | | | | LLVM should be -Wunused-private-field clean now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158103 91177308-0d34-0410-b5e6-96231b3b80d8
* Move RegisterClassInfo.h.Andrew Trick2012-06-0611-11/+11
| | | | | | | Allow targets to access this API. It's required for RegisterPressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158102 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead private member variables from gtest.Benjamin Kramer2012-06-062-3/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158101 91177308-0d34-0410-b5e6-96231b3b80d8
* Move RegisterPressure.h.Andrew Trick2012-06-064-3/+3
| | | | | | | Make it a general utility for use by Targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158097 91177308-0d34-0410-b5e6-96231b3b80d8
* Round 2 of dead private variable removal.Benjamin Kramer2012-06-0618-51/+19
| | | | | | | | LLVM is now -Wunused-private-field clean except for - lib/MC/MCDisassembler/Disassembler.h. Not sure why it keeps all those unaccessible fields. - gtest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158096 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer2012-06-0624-45/+21
| | | | | | | | There are some that I didn't remove this round because they looked like obvious stubs. There are dead variables in gtest too, they should be fixed upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for dynamic stack realignment in the presence of dynamic allocas onChad Rosier2012-06-066-16/+263
| | | | | | | | X86. rdar://11496434 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158087 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix combine of uno && ord -> false so that the ordering of the fcmps doesn'tChad Rosier2012-06-062-1/+13
| | | | | | | | matter. rdar://11579835 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158084 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead debug option -disable-rematerialization.Jakob Stoklund Olesen2012-06-061-4/+0
| | | | | | | Remat has been stable for years, and it isn't done by LiveIntervalAnalysis any longer. (See LiveRangeEdit). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158079 91177308-0d34-0410-b5e6-96231b3b80d8
* Grab-bag of reassociate tweaks. Unify handling of dead instructions andDuncan Sands2012-06-062-127/+117
| | | | | | | | | | instructions to reoptimize. Exploit this to more systematically eliminate dead instructions (this isn't very useful in practice but is convenient for analysing some testcase I am working on). No need for WeakVH any more: use an AssertingVH instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158073 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop leaking RegScavengers from TailDuplication.Benjamin Kramer2012-06-061-3/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158069 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct decoder for T1 conditional B encodingRichard Barton2012-06-062-3/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158055 91177308-0d34-0410-b5e6-96231b3b80d8
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