aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Reuse the enum names from X86Desc in the X86Disassembler.Benjamin Kramer2012-02-116-16/+38
| | | | | | | This requires some gymnastics to make it available for C code. Remove the names from the disassembler tables, making them relocation free. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150303 91177308-0d34-0410-b5e6-96231b3b80d8
* Document the new module flags.Bill Wendling2012-02-111-0/+126
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150301 91177308-0d34-0410-b5e6-96231b3b80d8
* [WIP] Initial code for module flags.Bill Wendling2012-02-1115-5/+382
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Module flags are key-value pairs associated with the module. They include a 'behavior' value, indicating how module flags react when mergine two files. Normally, it's just the union of the two module flags. But if two module flags have the same key, then the resulting flags are dictated by the behaviors. Allowable behaviors are: Error Emits an error if two values disagree. Warning Emits a warning if two values disagree. Require Emits an error when the specified value is not present or doesn't have the specified value. It is an error for two (or more) llvm.module.flags with the same ID to have the Require behavior but different values. There may be multiple Require flags per ID. Override Uses the specified value if the two values disagree. It is an error for two (or more) llvm.module.flags with the same ID to have the Override behavior but different values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150300 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some patterns for matching vector_shuffle instructions since ↵Craig Topper2012-02-112-78/+16
| | | | | | vector_shuffles should be custom lowered before isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150299 91177308-0d34-0410-b5e6-96231b3b80d8
* Add TargetPassConfig hooks for scheduling/bundling.Andrew Trick2012-02-112-7/+63
| | | | | | | | | In case the MachineScheduling pass I'm working on doesn't work well for another target, they can completely override it. This also adds a hook immediately after the RegAlloc pass to cleanup immediately after vregs go away. We may want to fold it into the postRA hook later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150298 91177308-0d34-0410-b5e6-96231b3b80d8
* commentAndrew Trick2012-02-111-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150297 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix shuffle lowering code to stop creating temporary DAG nodes to do shuffle ↵Craig Topper2012-02-111-36/+23
| | | | | | mask checks on. This seemed to be confusing things such that vector_shuffle ops to got through to iselection. This is another step towards removing the vector_shuffle handling patterns from isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150296 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow Post-RA LICM to hoist reserved register reads.Jakob Stoklund Olesen2012-02-111-0/+11
| | | | | | | | When using register masks, registers like %rip are clobbered by the register mask. LICM should still be able to hoist instructions reading %rip from a loop containing calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150288 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle register masks in local live range splitting.Jakob Stoklund Olesen2012-02-111-0/+25
| | | | | | | Again the goal is to produce identical assembly with register mask operands enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150287 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't read PreRegAlloc before it is initialized.Jakob Stoklund Olesen2012-02-111-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150286 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r150222, as the clang driver now handles this properly.Jim Grosbach2012-02-101-11/+3
| | | | | | | | Now that the clang driver passes the CPU and feature information to the backend when processing assembly files (150273), this isn't necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150274 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up comment.Jakob Stoklund Olesen2012-02-101-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150262 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a static MachineOperand::clobbersPhysReg().Jakob Stoklund Olesen2012-02-102-11/+14
| | | | | | | | It can be necessary to detach a register mask pointer from its MachineOperand. This method is convenient for checking clobbered physregs on a detached bitmask pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150261 91177308-0d34-0410-b5e6-96231b3b80d8
* Add register mask support to InterferenceCache.Jakob Stoklund Olesen2012-02-103-5/+42
| | | | | | | | | | | | | | | | This makes global live range splitting behave identically with and without register mask operands. This is not necessarily the best way of using register masks for live range splitting. It would be more efficient to first split global live ranges around calls (i.e., register masks), and reserve the fine grained per-physreg interference guidance for global live ranges that do not cross calls. For now the goal is to produce identical assembly when enabling register masks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150259 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused variable.Jakob Stoklund Olesen2012-02-101-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150258 91177308-0d34-0410-b5e6-96231b3b80d8
* Added description of invariant.load metadata to LangRef. It was added to ↵Pete Cooper2012-02-101-1/+9
| | | | | | the compiler in r144100 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150257 91177308-0d34-0410-b5e6-96231b3b80d8
* Make valgrind happy.Jason W Kim2012-02-101-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150251 91177308-0d34-0410-b5e6-96231b3b80d8
* Update BBVectorize to use aliasesUnknownInst.Hal Finkel2012-02-102-9/+247
| | | | | | | | This allows BBVectorize to check the "unknown instruction" list in the alias sets. This is important to prevent instruction fusing from reordering function calls. Resolves PR11920. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150250 91177308-0d34-0410-b5e6-96231b3b80d8
* Have AliasSet::aliasesUnknownInst use pointer TBAA info when availableHal Finkel2012-02-101-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150249 91177308-0d34-0410-b5e6-96231b3b80d8
* Make aliasesPointer and aliasesUnknownInst public members of AliasSet.Hal Finkel2012-02-101-0/+1
| | | | | | | | These query functions are safe for external use and, furthermore, are the only way to make queries against the "unknown instructions" array. BBVectorize will use these functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150248 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR11948: the result type of an icmp may be a vector of boolean -Duncan Sands2012-02-102-0/+12
| | | | | | | don't assume it is a boolean. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150247 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert commit 149912 (lattner) and add a testcase that shows the problem (whichDuncan Sands2012-02-102-1/+31
| | | | | | | | | | | is that patterns no longer match for vectors of booleans, because you only get ConstantDataVector when the vector element type is i8, i16, etc, not when it is i1). Original commit message: Remove some dead code and tidy things up now that vectors use ConstantDataVector instead of always using ConstantVector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150246 91177308-0d34-0410-b5e6-96231b3b80d8
* Put instruction names into an indexed string table on the side, removing a ↵Benjamin Kramer2012-02-105-14/+39
| | | | | | | | | pointer from MCInstrDesc. Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150245 91177308-0d34-0410-b5e6-96231b3b80d8
* comment grammarAndrew Trick2012-02-101-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150233 91177308-0d34-0410-b5e6-96231b3b80d8
* update --enable-targets listJia Liu2012-02-101-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150229 91177308-0d34-0410-b5e6-96231b3b80d8
* unnecessary includeAndrew Trick2012-02-101-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150228 91177308-0d34-0410-b5e6-96231b3b80d8
* PTX no longer needs to provide its own backend.Andrew Trick2012-02-102-255/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150227 91177308-0d34-0410-b5e6-96231b3b80d8
* RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick2012-02-1024-134/+180
| | | | | | | | | | | | | | | | Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2012-02-101-11/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150225 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused 'isAlias' parameter.Lang Hames2012-02-102-9/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150224 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM on darwin, v6 implies the presence of VFP for the assembler.Jim Grosbach2012-02-101-3/+11
| | | | | | rdar://10838899 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150222 91177308-0d34-0410-b5e6-96231b3b80d8
* Constrain the regmask search space for local live ranges.Jakob Stoklund Olesen2012-02-101-3/+13
| | | | | | | When checking a local live range for interference, restrict the binary search to the single block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150220 91177308-0d34-0410-b5e6-96231b3b80d8
* Cache basic block boundaries for faster RegMaskSlots access.Jakob Stoklund Olesen2012-02-102-1/+36
| | | | | | | Provide API to get a list of register mask slots and bits in a basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150219 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize LiveIntervals::intervalIsInOneMBB().Jakob Stoklund Olesen2012-02-102-20/+26
| | | | | | | | No looping and binary searches necessary. Return a pointer to the containing block instead of just a bool. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150218 91177308-0d34-0410-b5e6-96231b3b80d8
* Cache iterators. Some of these are expensive to create.Benjamin Kramer2012-02-101-14/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150214 91177308-0d34-0410-b5e6-96231b3b80d8
* Change default error_code ctor to a 'named ctor' so it's more self-documenting.David Blaikie2012-02-097-59/+58
| | | | | | | | | | | Unify default construction of error_code uses on this idiom so that users don't feel compelled to make static globals for naming convenience. (unfortunately I couldn't make the original ctor private as some APIs don't return their result, instead using an out parameter (that makes sense to default construct) - which is a bit of a pity. I did, however, find/fix some cases of unnecessary default construction of error_code before I hit the unfixable cases) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150197 91177308-0d34-0410-b5e6-96231b3b80d8
* Add register mask support to RAGreedy.Jakob Stoklund Olesen2012-02-091-2/+25
| | | | | | | | This only adds the interference checks required for correctness. We still need to take advantage of register masks for the interference driven live range splitting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150191 91177308-0d34-0410-b5e6-96231b3b80d8
* Now subprogram descriptors are not collected by llvm.dbg.sp NamedMDNode. ↵Devang Patel2012-02-091-2/+0
| | | | | | Update document to reflect this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150187 91177308-0d34-0410-b5e6-96231b3b80d8
* Tweak comment readability and grammar.Benjamin Kramer2012-02-091-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150183 91177308-0d34-0410-b5e6-96231b3b80d8
* Test for commit access.Sirish Pande2012-02-091-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150178 91177308-0d34-0410-b5e6-96231b3b80d8
* GlobalOpt: Be more aggressive about elminating side-effect free static dtors.Benjamin Kramer2012-02-092-6/+9
| | | | | | | | | GlobalOpt runs early in the pipeline (before inlining) and complex class hierarchies often introduce bitcasts or GEPs which weren't optimized away. Teach it to ignore side-effect free instructions instead of depending on other passes to remove them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150174 91177308-0d34-0410-b5e6-96231b3b80d8
* Store just the SimpleValueType in the generated VT tables for each register ↵Benjamin Kramer2012-02-092-4/+5
| | | | | | class, eliminating static ctors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150173 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the Name field in MCInstrDesc to the end, saving 8 bytes of padding per ↵Benjamin Kramer2012-02-092-3/+4
| | | | | | | | entry on x86_64. No change on i386. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150170 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the MC and disassembler about SoftFail, and hook it up to ↵James Molloy2012-02-094-2/+90
| | | | | | UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150169 91177308-0d34-0410-b5e6-96231b3b80d8
* More tweaks to get the size of the X86 disassembler tables down.Craig Topper2012-02-093-7/+35
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150167 91177308-0d34-0410-b5e6-96231b3b80d8
* Flatten some of the arrays in the X86 disassembler tables to reduce space ↵Craig Topper2012-02-094-45/+44
| | | | | | needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150161 91177308-0d34-0410-b5e6-96231b3b80d8
* Preserve physreg kills in MachineBasicBlock::SplitCriticalEdge.Lang Hames2012-02-091-4/+7
| | | | | | | | Failure to preserve kills was causing LiveIntervals to miss some EFLAGS live ranges. Unfortunately I've been unable to reduce a good test case yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150152 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86/atom-lea-sp.ll: Add explicit -mtriple=i686-linux.NAKAMURA Takumi2012-02-091-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150151 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix kill flags when moving instructions using LiveIntervals::moveInstr(...).Lang Hames2012-02-091-6/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150150 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove assertion. Not all use operands are reads.Lang Hames2012-02-091-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150149 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2024-09-19 18:54:34 +0000