aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and ↵Jyotsna Verma2013-03-229-494/+1948
| | | | | | word. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177747 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor out the DIFile parameter to DILexicalBlock to refer to the raw ↵David Blaikie2013-03-229-19/+9
| | | | | | file/directory pair git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177742 91177308-0d34-0410-b5e6-96231b3b80d8
* fix small doc typoEli Bendersky2013-03-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177737 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730Michel Danzer2013-03-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177736 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove ABI-duplicated call instruction patterns.Ulrich Weigand2013-03-228-148/+71
| | | | | | | | | | | | | | | | | | | | We currently have a duplicated set of call instruction patterns depending on the ABI to be followed (Darwin vs. Linux). This is a bit odd; while the different ABIs will result in different instruction sequences, the actual instructions themselves ought to be independent of the ABI. And in fact it turns out that the only nontrivial difference between the two sets of patterns is that in the PPC64 Linux ABI, the instruction used for indirect calls is marked to take X11 as extra input register (which is indeed used only with that ABI to hold an incoming environment pointer for nested functions). However, this does not need to be hard-coded at the .td pattern level; instead, the C++ code expanding calls can simply add that use, just like it adds uses for argument registers anyway. No change in generated code expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177735 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename memrr ptrreg and offreg components.Ulrich Weigand2013-03-222-22/+22
| | | | | | | | | | | | | Currently, the sub-operand of a memrr address that corresponds to what hardware considers the base register is called "offreg", while the sub-operand that corresponds to the offset is called "ptrreg". To avoid confusion, this patch simply swaps the named of those two sub-operands and updates all uses. No functional change is intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177734 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix swapped BasePtr and Offset in pre-inc memory addresses.Ulrich Weigand2013-03-224-20/+40
| | | | | | | | | | | | | | | | | | | | | | PPCTargetLowering::getPreIndexedAddressParts currently provides the base part of a memory address in the offset result, and the offset part in the base result. That swap is then undone again when an MI instruction is generated (in PPCDAGToDAGISel::Select for loads, and using .md Pat patterns for stores). This patch reverts this double swap, to make common code and back-end be in sync as to which part of the address is base and which is offset. To avoid performance regressions in certain cases, target code now checks whether the choice of base register would be rejected for pre-inc accesses by common code, and attempts to swap base and offset again in such cases. (Overall, this means that now pre-ice accesses are generated *more* frequently than before.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177733 91177308-0d34-0410-b5e6-96231b3b80d8
* Tighten iaddroff ComplexPattern.Ulrich Weigand2013-03-221-4/+4
| | | | | | | | | | | | | | | | | | | The iaddroff ComplexPattern is supposed to recognize displacement expressions that have been processed by a SelectAddressRegImm, which means it needs to accept TargetConstant and TargetGlobalAddress nodes. Currently, it erroneously also accepts some other nodes, in particular Constant and PPCISD::Lo. While this problem is currently latent, it would cause wrong-code bugs with a follow-on patch I'm about to commit, so this patch tightens the ComplexPattern. The equivalent change is made in PPCDAGToDAGISel::Select, where pre-inc load patterns are handled (as opposed to store patterns, the loads are handled in C++ code without making use of the .td ComplexPattern). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177732 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the xaddroff ComplexPattern.Ulrich Weigand2013-03-223-31/+18
| | | | | | | | | | | The xaddroff pattern is currently (mistakenly) used to recognize the *base* register in pre-inc store patterns. This patch replaces those uses by ptr_rc_nor0 (as is elsewhere done to match the base register of an address), and removes the now unused ComplexPattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177731 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsicsMichel Danzer2013-03-224-15/+5
| | | | | | | | | | | | | | | | | Fixes wrong lighting in some corner cases with r600g and radeonsi, e.g. manifested by failure of two piglit/glean tests and intermittent black patches in many apps. Tested on SI and RS880. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62012 [radeonsi] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58150 [r600g] NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177730 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] Change the way we report the alloca frame on stack-buff-overflow.Kostya Serebryany2013-03-221-8/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: the function name was stored by the compiler as a constant string and the run-time was printing it. Now: the PC is stored instead and the run-time prints the full symbolized frame. This adds a couple of instructions into every function with non-empty stack frame, but also reduces the binary size because we store less strings (I saw 2% size reduction). This change bumps the asan ABI version to v3. llvm part. Example of report (now): ==31711==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7fffa77cf1c5 at pc 0x41feb0 bp 0x7fffa77cefb0 sp 0x7fffa77cefa8 READ of size 1 at 0x7fffa77cf1c5 thread T0 #0 0x41feaf in Frame0(int, char*, char*, char*) stack-oob-frames.cc:20 #1 0x41f7ff in Frame1(int, char*, char*) stack-oob-frames.cc:24 #2 0x41f477 in Frame2(int, char*) stack-oob-frames.cc:28 #3 0x41f194 in Frame3(int) stack-oob-frames.cc:32 #4 0x41eee0 in main stack-oob-frames.cc:38 #5 0x7f0c5566f76c (/lib/x86_64-linux-gnu/libc.so.6+0x2176c) #6 0x41eb1c (/usr/local/google/kcc/llvm_cmake/a.out+0x41eb1c) Address 0x7fffa77cf1c5 is located in stack of thread T0 at offset 293 in frame #0 0x41f87f in Frame0(int, char*, char*, char*) stack-oob-frames.cc:12 <<<<<<<<<<<<<< this is new This frame has 6 object(s): [32, 36) 'frame.addr' [96, 104) 'a.addr' [160, 168) 'b.addr' [224, 232) 'c.addr' [288, 292) 's' [352, 360) 'd' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177724 91177308-0d34-0410-b5e6-96231b3b80d8
* tsan: fix the testDmitry Vyukov2013-03-221-1/+1
| | | | | | | | Add missed file from r177717 commit that adds __tsan_vptr_read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177719 91177308-0d34-0410-b5e6-96231b3b80d8
* tsan: handle vptr loads speciallyDmitry Vyukov2013-03-222-0/+23
| | | | | | | | | This is required to determine ctor/dtor vs virtual call races. http://llvm-reviews.chandlerc.com/D566 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177717 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix llvm::removeUnreachableBlocks to handle unreachable loops.Evgeniy Stepanov2013-03-222-12/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177713 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Improve the result bitvect type when folding (cmp pred (load ↵Arnaud A. de Grandmaison2013-03-224-11/+43
| | | | | | | | | | | | | | | (gep GV, i)) C) to a bit test. The original code used i32, and i64 if legal. This introduced unneeded casts when they aren't legal, or when the index variable i has another type. In order of preference: try to use i's type; use the smallest fitting legal type (using an added DataLayout method); default to i32. A testcase checks that this works when the index gep operand is i16. Patch by : Ahmed Bougacha <ahmed.bougacha@gmail.com> Reviewed by : Duncan git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177712 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove ScavengedRC from RegisterScavengingHal Finkel2013-03-222-8/+1
| | | | | | | ScavengedRC was a dead private variable (set, but not otherwise used). No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177708 91177308-0d34-0410-b5e6-96231b3b80d8
* Reorder the DIFile field in DILexicalBlock to become a prefix common with ↵David Blaikie2013-03-2245-95/+95
| | | | | | other DIScopes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177703 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the empty directory. Silly git-svn.Chandler Carruth2013-03-220-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177702 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the ARM-specific variant of this test. It's already covered byChandler Carruth2013-03-222-6/+0
| | | | | | | | | | the ARM build bots, and it adds a weird case to the test suite where a test uses as inputs files in the parent directory. Talked about this with Dave on IRC and he's fine with this approach even though it isn't optimal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177700 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce LLVM_STATIC_ASSERT macro, which expands to C/C++'s static_assert ↵Argyrios Kyrtzidis2013-03-221-0/+10
| | | | | | on compilers which support it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177699 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r177543: Add timing of the IR parsing code with a newChandler Carruth2013-03-223-29/+0
| | | | | | | | | | | | | | | -time-ir-parsing flag This breaks the layering of the Support library. We can't add an implementation side to IRReader because it refers directly to entities only accessible as part of the IR, AsmParser, and BitcodeReader libraries. It can only be used in a context where all of those libraries will be available. We'll need to find some other way to get this functionality, and hopefully solve the long-standing layering problem of IRReader.h... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177695 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the invalid opcode for Mips branch instructions in the assemblerJack Carter2013-03-222-16/+18
| | | | | | | | | | | | | | | | | | For mips a branch an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. Previously, the code generator did not perform the shift of the immediate branch offset which resulted in wrong instruction opcode. This patch fixes the issue. Contributor: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177687 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch that enables the Mips assembler to use symbols for offset for ↵Jack Carter2013-03-223-17/+176
| | | | | | | | | | | | | | | instructions This patch uses the generated instruction info tables to identify memory/load store instructions. After successful matching and based on the operand type and size, it generates additional instructions to the output. Contributor: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177685 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the G8RC_NOX0_and_GPRC_NOR0 PPC register classHal Finkel2013-03-213-7/+12
| | | | | | | | | | | | As Jakob pointed out in his review of r177423, having a shared ZERO register between the 32- and 64-bit register classes causes this odd G8RC_NOX0_and_GPRC_NOR0 class to be created. As recommended, this adds a ZERO8 register which differentiates the 32- and 64-bit zeros. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177683 91177308-0d34-0410-b5e6-96231b3b80d8
* Add TableGen ctags(1) emitter and helper script.Sean Silva2013-03-215-1/+561
| | | | | | | | | | | | | | | | | | | | | To use this in conjunction with exuberant ctags to generate a single combined tags file, run tblgen first and then $ ctags --append [...] Since some identifiers have corresponding definitions in C++ code, it can be useful (if using vim) to also use cscope, and :set cscopetagorder=1 so that :tag X will preferentially select the tablegen symbol, while :cscope find g X will always find the C++ symbol. Patch by Kevin Schoedel! (a couple small formatting changes courtesy of clang-format) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177682 91177308-0d34-0410-b5e6-96231b3b80d8
* Always forward 'resume' instructions to the outter landing pad.Bill Wendling2013-03-211-16/+39
| | | | | | | | | | | | | | | | | | How did this ever work? Basically, if you have a function that's inlined into the caller, it may not have any 'call' instructions, but any 'resume' instructions it may have should still be forwarded to the outer (caller's) landing pad. This requires that all of the 'landingpad' instructions in the callee have their clauses merged with the caller's outer 'landingpad' instruction (hence the bit of ugly code in the `forwardResume' method). Testcase in a follow commit to the test-suite repository. <rdar://problem/13360379> & PR15555 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177680 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a register-class comparison bug in PPCCTRLoopsHal Finkel2013-03-214-20/+3
| | | | | | | | | Thanks to Jakob for isolating the underlying problem from the test case in r177423. The original commit had introduced asymmetric copy operations, but these turned out to be a work-around to the real problem (the use of == instead of hasSubClassEq in PPCCTRLoops). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177679 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor the filename/directory information in DISubprogram to refer ↵David Blaikie2013-03-215-17/+5
| | | | | | directly to the pair rather than the DIFile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177677 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a query to tell if a landing pad has a catch-all.Bill Wendling2013-03-212-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177675 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the DIFile in DISubprogram to the beginning to be a common prefix along ↵David Blaikie2013-03-2128-101/+101
| | | | | | with other DIScopes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177674 91177308-0d34-0410-b5e6-96231b3b80d8
* <rdar://problem/13477190> On Darwin, use DARWIN_USER_TEMP_DIR or ↵Douglas Gregor2013-03-211-0/+24
| | | | | | | | | | | DARWIN_USER_CACHE_DIR for the system temporary directory. The DARWIN_USER_TEMP_DIR and DARWIN_USER_CACHE_DIR configuration settings are more idiomatic for Darwin than the TMPDIR environment variable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177669 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch enables the Mips .set directive to define aliasesJack Carter2013-03-212-6/+99
| | | | | | | | | | | | | | | | | | | The .set directive in the Mips the assembler can be used to set the value of a symbol to an expression. This changes the symbol's value and type to conform to the expression's. Syntax: .set symbol, expression This patch implements the parsing of the above syntax and enables the parser to use defined symbols when parsing operands. Contributor: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177667 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement builtin_{setjmp/longjmp} on PPCHal Finkel2013-03-2110-0/+475
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements SJLJ lowering on PPC, making the Clang functions __builtin_{setjmp/longjmp} functional on PPC platforms. The implementation strategy is similar to that on X86, with the exception that a branch-and-link variant is used to get the right jump address. Credit goes to Bill Schmidt for suggesting the use of the unconditional bcl form (instead of the regular bl instruction) to limit return-address-cache pollution. Benchmarking the speed at -O3 of: static jmp_buf env_sigill; void foo() { __builtin_longjmp(env_sigill,1); } main() { ... for (int i = 0; i < c; ++i) { if (__builtin_setjmp(env_sigill)) { goto done; } else { foo(); } done:; } ... } vs. the same code using the libc setjmp/longjmp functions on a P7 shows that this builtin implementation is ~4x faster with Altivec enabled and ~7.25x faster with Altivec disabled. This comparison is somewhat unfair because the libc version must also save/restore the VSX registers which we don't yet support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177666 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Darwin NEON FP and increase coverageRenato Golin2013-03-216-13/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177664 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused field in DISubprogramDavid Blaikie2013-03-2190-209/+209
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177661 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for spilling VRSAVE on PPCHal Finkel2013-03-215-1/+124
| | | | | | | | | | Although there is only one Altivec VRSAVE register, it is a member of a register class, and we need the ability to spill it. Because this register is normally callee-preserved and handled by special code this has never before been necessary. However, this capability will be required by a forthcoming commit adding SjLj support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177654 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct PPC FRAMEADDR lowering using a pseudo-registerHal Finkel2013-03-216-9/+97
| | | | | | | | | | | | | | | | The old code used to lower FRAMEADDR tried to replicate the logic in the real frame-lowering code that determines whether or not the frame pointer (r31) will be used. When it seemed as through the frame pointer would not be used, the stack pointer (r1) was used instead. Unfortunately, because the stack size is not yet known, this does not work. Instead, this change introduces new always-reserved pseudo-registers (FP and FP8) that are replaced during prologue insertion with the real frame-pointer register (either r1 or r31). It is important that this intrinsic always return a valid frame address because it is used by Clang to store the frame address as part of code generation for __builtin_setjmp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177653 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid NEON SP-FP unless unsafe-math or DarwinRenato Golin2013-03-2112-20/+143
| | | | | | | | | | NEON is not IEEE 754 compliant, so we should avoid lowering single-precision floating point operations with NEON unless unsafe-math is turned on. The equivalent VFP instructions are IEEE 754 compliant, but in some cores they're much slower, so some archs/OSs might still request it to be on by default, such as Swift and Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177651 91177308-0d34-0410-b5e6-96231b3b80d8
* Update some EH tests that were violating the new EH model.Bill Wendling2013-03-213-6/+16
| | | | | | | | The landingpad instruction needs to be the first non-PHI instruction in the unwind destination block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177650 91177308-0d34-0410-b5e6-96231b3b80d8
* Hoist the definition of getTypeSizeInBits to be inlinable and in theChandler Carruth2013-03-212-41/+45
| | | | | | | | | | | | | | | | | | header. This method is called in the hot path for *many* passes, SROA is what caught my interest. A common pattern is that which branch of the switch should be taken is known in the callsite and so it is a very good candidate for inlining and simplification. Moving it into the header allows the optimizer to fold a lot of boring, repeatitive code in callers of this routine. I'm seeing pretty significant speedups in parts of SROA and I suspect other passes will see similar speedups if they end up working with type sizes frequently. I've not seen any significant growth of the binaries as a consequence, but let me know if you see anything suspicious here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177632 91177308-0d34-0410-b5e6-96231b3b80d8
* [SROA] Prefix names using a custom IRBuilder inserter.Chandler Carruth2013-03-211-88/+108
| | | | | | | | | | | | | | | | | | | The key part of this is ensuring that name prefixes remain in a Twine form until we get to a point where we can nuke them under NDEBUG. This is tricky using the old APIs as they played fast and loose with Twine, which is prone to serious error. The inserter is much cleaner as it is actually in the call stack leading to the setName call, and so has a good opportunity to prepend the prefix. This matters more than you might imagine because most runs over an alloca find a single partition, and rewrite 3 or 4 instructions referring to it. As a consequence doing this lazily and exclusively with Twine allows the optimizer to delete more of it and shaves another 2% to 3% off of the release build's SROA run time for PR15412. I also think the APIs are cleaner, and the use of Twine is more reliable, so I consider it a win-win despite the churn required to reach this state. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177631 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Add an option to disable poisoning of shadow for undef values.Evgeniy Stepanov2013-03-211-2/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177630 91177308-0d34-0410-b5e6-96231b3b80d8
* simplify-libcalls: Removed unused variableMeador Inge2013-03-211-2/+0
| | | | | | | The 'Modified' variable should have been removed from SimplifyLibCalls in r177619, but was missed. This commit removes it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177622 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix missing std::. Not sure how this compiles for anyone else.Matt Arsenault2013-03-212-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177620 91177308-0d34-0410-b5e6-96231b3b80d8
* Move library call prototype attribute inference to functionattrsMeador Inge2013-03-217-725/+780
| | | | | | | | | | | | The simplify-libcalls pass implemented a doInitialization hook to infer function prototype attributes for well-known functions. Given that the simplify-libcalls pass is going away *and* that the functionattrs pass is already in place to deduce function attributes, I am moving this logic to the functionattrs pass. This approach was discussed during patch review: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121126/157465.html. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177619 91177308-0d34-0410-b5e6-96231b3b80d8
* Removing unused DISubprogram::getFileDavid Blaikie2013-03-211-4/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177614 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a WriteMicrocoded for ancient microcoded instructions.Jakob Stoklund Olesen2013-03-212-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177611 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug info: refactor the first field of DICompileUnit to be a raw ↵David Blaikie2013-03-2043-59/+54
| | | | | | | | file/directory pair This removes the DICompileUnit special case from DIScope. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177610 91177308-0d34-0410-b5e6-96231b3b80d8
* Use pre-inc, pre-dec when possible.Jakub Staszak2013-03-203-12/+12
| | | | | | | They are generally faster (at least not slower) than post-inc, post-dec. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177608 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove 'else' after 'return'.Jakub Staszak2013-03-201-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177607 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-03-21 11:50:47 +0000