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* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-2611-326/+187
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding the missing implementation of Bitfield's "clear" and "insert".Shih-wei Liao2010-05-261-4/+9
| | | | | | | Fixing http://llvm.org/bugs/show_bug.cgi?id=7222. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104653 91177308-0d34-0410-b5e6-96231b3b80d8
* To handle s* registers in emitVFPLoadStoreMultipleInstruction().Shih-wei Liao2010-05-261-7/+12
| | | | | | | Fixing http://llvm.org/bugs/show_bug.cgi?id=7221. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104652 91177308-0d34-0410-b5e6-96231b3b80d8
* Start adding mach-o tls reloc support.Eric Christopher2010-05-263-3/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104651 91177308-0d34-0410-b5e6-96231b3b80d8
* Drop the SuperregHashTable. It is essentially the same as SubregHashTable.Jakob Stoklund Olesen2010-05-253-103/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104650 91177308-0d34-0410-b5e6-96231b3b80d8
* First cut at supporting .debug_loc section. Devang Patel2010-05-254-87/+492
| | | | | | | This is used to track variable information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104649 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly promote operands when optimizing a single-character memcmp.Benjamin Kramer2010-05-252-4/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104648 91177308-0d34-0410-b5e6-96231b3b80d8
* Constify function.Bill Wendling2010-05-251-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104646 91177308-0d34-0410-b5e6-96231b3b80d8
* Do one map lookup instead of two.Dan Gohman2010-05-251-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104645 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a missing newline in debug output.Dan Gohman2010-05-251-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104644 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the verbose asm output up a bit so it can be used in the special casesEric Christopher2010-05-251-5/+6
| | | | | | | as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104642 91177308-0d34-0410-b5e6-96231b3b80d8
* Okay, bear with me here...Bill Wendling2010-05-251-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If you have a setjmp/longjmp situation, it's possible for stack slot coloring to reuse a stack slot before it's really dead. For instance, if we have something like this: 1: y = g; x = sigsetjmp(env, 0); switch (x) { case 1: /* ... */ goto run; case 0: run: do_run(); /* marked as "no return" */ break; case 3: if (...) { /* ... */ goto run; } /* ... */ break; } 2: g = y; "y" may be put onto the stack, so the expression "g = y" is relying upon the fact that the stack slot containing "y" isn't modified between (1) and (2). But it can be, because of the "no return" calls in there. A longjmp might come back with 3, modify the stack slot, and then go to case 0. And it's perfectly acceptable to reuse the stack slot there because there's no CFG flow from case 3 to (2). The fix is to disable certain optimizations in these situations. Ideally, we'd disable them for all "returns twice" functions. But we don't support that attribute. Check for "setjmp" and "sigsetjmp" instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104640 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for initialized global data for darwin tls. Update commentsEric Christopher2010-05-253-94/+144
| | | | | | | and testcases accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104635 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed the encoding of X86 floating point stack operations where both operandsKevin Enderby2010-05-252-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | are st(0). These can be encoded using an opcode for storing in st(0) or using an opcode for storing in st(i), where i can also be 0. To allow testing with the darwin assembler and get a matching binary the opcode for storing in st(0) is now used. To do this the same logical trick is use from the darwin assembler in converting things like this: fmul %st(0), %st into this: fmul %st(0) by looking for the second operand being X86::ST0 for specific floating point mnemonics then removing the second X86::ST0 operand. This also has the add benefit to allow things like: fmul %st(1), %st that llvm-mc did not assemble. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104634 91177308-0d34-0410-b5e6-96231b3b80d8
* Removing test; Chris thinks it's better to have theDale Johannesen2010-05-251-2718/+0
| | | | | | | | bug go untested than have a testcase this large. So be it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104632 91177308-0d34-0410-b5e6-96231b3b80d8
* Separate unrelated cases that once shared a numeric valueJakob Stoklund Olesen2010-05-251-9/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104629 91177308-0d34-0410-b5e6-96231b3b80d8
* Print symbolic SubRegIndex names on machine operands.Jakob Stoklund Olesen2010-05-254-4/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove NumberHack entirely.Jakob Stoklund Olesen2010-05-258-52/+45
| | | | | | | SubRegIndex instances are now numbered uniquely the same way Register instances are - in lexicographical order by name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/X86: Add a hack to allow recognizing 'cmpltps' and friends.Daniel Dunbar2010-05-252-1/+70
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104626 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix another variant of PR 7191. Also add a testcaseDale Johannesen2010-05-252-1/+2723
| | | | | | | | | | Mon Ping provided; unfortunately bugpoint failed to reduce it, but I think it's important to have a test for this in the suite. 8023512. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104624 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}.Daniel Dunbar2010-05-252-0/+67
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104622 91177308-0d34-0410-b5e6-96231b3b80d8
* The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is requiredKevin Enderby2010-05-252-1/+7
| | | | | | | for the 64-bit version of the Bit Test instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104621 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR 7191. I have been unable to create a .ll file that fails, sorry.Dale Johannesen2010-05-251-2/+10
| | | | | | | | | (oye, a word which should be better known to people writing tree traversals, means grandchild.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104619 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure aeskeygenassist uses an unsigned immediate field.Eric Christopher2010-05-253-37/+41
| | | | | | | Fixes rdar://8017638 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104617 91177308-0d34-0410-b5e6-96231b3b80d8
* Ignore NumberHack and give each SubRegIndex instance a unique enum value ↵Jakob Stoklund Olesen2010-05-253-6/+9
| | | | | | | | | | | instead. This passes lit tests, but I'll give it a go through the buildbots to smoke out any remaining places that depend on the old SubRegIndex numbering. Then I'll remove NumberHack entirely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104615 91177308-0d34-0410-b5e6-96231b3b80d8
* Use enums instead of literals for SystemZ subregistersJakob Stoklund Olesen2010-05-251-11/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104612 91177308-0d34-0410-b5e6-96231b3b80d8
* Use enums instead of literals for X86 subregisters.Jakob Stoklund Olesen2010-05-252-11/+10
| | | | | | | The cases in getMatchingSuperRegClass cannot be broken up until the enums have unique values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104611 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing implementation to the materialization of VFP misc. instructions ↵Zonr Chang2010-05-251-0/+43
| | | | | | (vmrs, vmsr and vmov (immediate)) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104588 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support to MOVimm32 using movt/movw for ARM JITZonr Chang2010-05-253-2/+113
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104587 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated.Bob Wilson2010-05-251-6/+6
| | | | | | | | I don't know of any particular reason why that would be important, but neither can I see any reason to disallow it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104583 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix up instruction classes for Thumb2 RSB instructions to be consistent withBob Wilson2010-05-251-15/+15
| | | | | | | | Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the condition codes, and allow RSBS instructions to be predicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104582 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up indentation.Bob Wilson2010-05-251-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104580 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable invalid coalescer assertion.Jakob Stoklund Olesen2010-05-251-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104574 91177308-0d34-0410-b5e6-96231b3b80d8
* Use enums instead of literals in the ARM backend.Jakob Stoklund Olesen2010-05-252-18/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104573 91177308-0d34-0410-b5e6-96231b3b80d8
* Print out the name of the function during SSC.Bill Wendling2010-05-241-1/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104572 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch SubRegSet to using symbolic SubRegIndicesJakob Stoklund Olesen2010-05-249-189/+197
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow Thumb2 MVN instructions to set condition codes. The immediate operandBob Wilson2010-05-241-5/+5
| | | | | | | version of t2MVN already allowed that, but not the register versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104570 91177308-0d34-0410-b5e6-96231b3b80d8
* diaggroup categories should take precedence over diag-specific groups.Chris Lattner2010-05-241-8/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104567 91177308-0d34-0410-b5e6-96231b3b80d8
* Lose the dummiesJakob Stoklund Olesen2010-05-241-22/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104564 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-2413-163/+207
| | | | | | | | | | | structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid adding duplicate function live-in's.Evan Cheng2010-05-243-2/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104560 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an mmx movd encoding.Dan Gohman2010-05-242-4/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104552 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/X86: Add aliases for CMOVcc variants.Kevin Enderby2010-05-242-0/+143
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104549 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up some extra whitespace.Bob Wilson2010-05-241-12/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104544 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 RSBS instructions were being printed without the 'S' suffix.Bob Wilson2010-05-242-6/+13
| | | | | | | | Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR output and 'S' suffix in the same way as T2I_bin_s_irs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104531 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not emit line number entries for unknown debug values.Devang Patel2010-05-241-0/+3
| | | | | | | This fixes recent regression in store.exp from gdb testsuite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104524 91177308-0d34-0410-b5e6-96231b3b80d8
* LR is in GPR, not tGPR even in Thumb1 mode.Evan Cheng2010-05-242-4/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
* Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices areJakob Stoklund Olesen2010-05-241-0/+7
| | | | | | never used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104517 91177308-0d34-0410-b5e6-96231b3b80d8
* Use SubRegIndex in SystemZ.Jakob Stoklund Olesen2010-05-243-17/+10
| | | | | | Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104515 91177308-0d34-0410-b5e6-96231b3b80d8
* SubRegIndex'ize MipsJakob Stoklund Olesen2010-05-243-17/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104514 91177308-0d34-0410-b5e6-96231b3b80d8
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