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* [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from ↵Daniel Sanders2013-10-113-16/+193
| | | | | | normal IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192438 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not ↵Daniel Sanders2013-10-113-4/+51
| | | | | | intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192435 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target fix bug in emitArrayBound() causing segmentation faultRobert Lytton2013-10-113-7/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192434 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target does not emit '.hidden' or '.protected' attributesRobert Lytton2013-10-112-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192433 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: fix bug in XCoreLowerThreadLocal.cppRobert Lytton2013-10-112-10/+60
| | | | | | | | | When a ConstantExpr which uses a thread local is part of a PHI node instruction, the insruction that replaces the ConstantExpr must be inserted in the predecessor block, in front of the terminator instruction. If the predecessor block has multiple successors, the edge is first split. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192432 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: add XCoreTargetLowering::isZExtFree()Robert Lytton2013-10-113-0/+37
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192431 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not ↵Daniel Sanders2013-10-113-4/+51
| | | | | | intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192430 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] ↵Daniel Sanders2013-10-113-12/+143
| | | | | | from normal IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192429 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove another unnecessary filter from the disassembler.Craig Topper2013-10-111-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192425 91177308-0d34-0410-b5e6-96231b3b80d8
* LiveRangeCalc.h: Update a description corresponding to r192396. ↵NAKAMURA Takumi2013-10-111-1/+1
| | | | | | [-Wdocumentation] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192421 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement aarch64 neon instruction set AdvSIMD (copy).Kevin Qin2013-10-116-56/+875
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192410 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typoMatt Arsenault2013-10-101-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192406 91177308-0d34-0410-b5e6-96231b3b80d8
* Tests: Do not unnecessarily depend on kill commentsMatthias Braun2013-10-101-9/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192404 91177308-0d34-0410-b5e6-96231b3b80d8
* Tests: Use CHECK-LABEL where possibleMatthias Braun2013-10-104-15/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192403 91177308-0d34-0410-b5e6-96231b3b80d8
* Print register in LiveInterval::print()Matthias Braun2013-10-107-23/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192398 91177308-0d34-0410-b5e6-96231b3b80d8
* Represent RegUnit liveness with LiveRange instanceMatthias Braun2013-10-1013-129/+132
| | | | | | | Previously LiveInterval has been used, but having a spill weight and register number is unnecessary for a register unit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192397 91177308-0d34-0410-b5e6-96231b3b80d8
* Work on LiveRange instead of LiveInterval where possibleMatthias Braun2013-10-106-69/+63
| | | | | | | Also change some pointer arguments to references at some places where 0-pointers are not allowed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192396 91177308-0d34-0410-b5e6-96231b3b80d8
* Change MachineVerifier to work on LiveRange + LiveIntervalMatthias Braun2013-10-101-92/+117
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192395 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass LiveQueryResult by valueMatthias Braun2013-10-1010-117/+125
| | | | | | | This makes the API a bit more natural to use and makes it easier to make LiveRanges implementation details private. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192394 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor LiveInterval: introduce new LiveRange classMatthias Braun2013-10-104-217/+235
| | | | | | | | | | LiveRange just manages a list of segments and a list of value numbers now as LiveInterval did previously, but without having details like spill weight or a fixed register number. LiveInterval is now a subclass of LiveRange and simply adds the spill weight and the register number. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192393 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename LiveRange to LiveInterval::SegmentMatthias Braun2013-10-1016-369/+366
| | | | | | | | The Segment struct contains a single interval; multiple instances of this struct are used to construct a live range, but the struct is not a live range by itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192392 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename parameter: defined regs are not incoming.Matthias Braun2013-10-102-18/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192391 91177308-0d34-0410-b5e6-96231b3b80d8
* test commitSriram Murali2013-10-101-2/+4
| | | | | | | | - fix comments on vector type legalization git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192389 91177308-0d34-0410-b5e6-96231b3b80d8
* Use getPointerSizeInBits() rather than 8 * getPointerSize()Matt Arsenault2013-10-101-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192386 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix grammar / missing wordsMatt Arsenault2013-10-101-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192380 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: In DIBuilder, the context field of subprogram is updated to useManman Ren2013-10-108-12/+56
| | | | | | | | | DIScopeRef. A paired commit at clang is required due to changes to DIBuilder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192378 91177308-0d34-0410-b5e6-96231b3b80d8
* Add comments to debug info testing case.Manman Ren2013-10-101-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192376 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix trunc i64 to i32 on SIMatt Arsenault2013-10-102-0/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192375 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide msbuild integration for vs2013.Hans Wennborg2013-10-104-1/+49
| | | | | | Patch by Josh Samuel! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192371 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix msbuild integration install script.Hans Wennborg2013-10-101-2/+5
| | | | | | | We previously failed to check whether the SUCCESS variable was set, and would thus always exit with a failure if vs2012 didn't exist. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192370 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Implement SIInstrInfo::verifyInstruction() for VOP*Tom Stellard2013-10-105-4/+142
| | | | | | | The function is used by the machine verifier and checks that VOP* instructions have legal operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192367 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use -verify-machineinstrs for most testsTom Stellard2013-10-1084-86/+86
| | | | | | | | | | | We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192366 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Define a separate MIMG instruction for each possible output value typeTom Stellard2013-10-105-35/+90
| | | | | | | | | | | | | During instruction selection, we rewrite the destination register class for MIMG instructions based on their writemasks. This creates machine verifier errors since the new register class does not match the register class in the MIMG instruction definition. We can avoid this by defining different MIMG instructions for each possible destination type and then switching to the correct instruction when we change the register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192365 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Mark the EXEC register as reservedTom Stellard2013-10-101-0/+1
| | | | | | | | | This prevents the machine verifier from complaining about uses of an undefined physical register. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192364 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use StructurizeCFGPass for non SI targetsTom Stellard2013-10-106-2/+18
| | | | | | | | | | | | | | | StructurizeCFG pass allows to make complex cfg reducible ; it allows a lot of shader from shadertoy (which exhibits complex control flow constructs) to works correctly with respect to CFG handling (and allow us to detect potential bug in other part of the backend). We provide a cmd line argument to disable the pass for debug purpose. Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192363 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-1015-3/+2827
| | | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192361 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Implement AArch64 vector load/store multiple N-element structure ↵Rafael Espindola2013-10-1015-2808/+3
| | | | | | | | class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)." This reverts commit r192352. It broke the build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192354 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-1015-3/+2808
| | | | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192352 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Put isV8EligibleForIT into the llvm namespace. While there make it inline.Benjamin Kramer2013-10-101-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192350 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable function padding to get this test to pass on atom.Benjamin Kramer2013-10-101-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192348 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: correct liveness flags during ARMLoadStoreOptTim Northover2013-10-102-0/+117
| | | | | | | | | | | | | | | | | | | | | | When we had a sequence like: s1 = VLDRS [r0, 1], Q0<imp-def> s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def> s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def> s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def> we were gathering the {s0, s1} loads below the s3 load. This is fine, but confused the verifier since now the s3 load had Q0<imp-use> with no definition above it. This should mark such uses <undef> as well. The liveness structure at the beginning and end of the block is unaffected, and the true sN definitions should prevent any dodgy reorderings being introduced elsewhere. rdar://problem/15124449 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192344 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow non-AVX form of pmovmskb to take a GR64 operand.Craig Topper2013-10-102-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192341 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove duplicate instructions.Craig Topper2013-10-101-16/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192340 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables.Craig Topper2013-10-101-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192339 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Do not generate INS/EXT nodes if target does not have support forAkira Hatanaka2013-10-093-17/+25
| | | | | | | | ins/ext. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192330 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "llvm-c: Make target initializer functions external functions in lib."Rui Ueyama2013-10-093-55/+36
| | | | | | | | This reverts commit r192316. The original change introduced circular dependencies between libTarget and backends. That would broke a build unless link everything into one big binary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192329 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: In DIBuilder, the context and type fields of template_type andManman Ren2013-10-095-54/+76
| | | | | | | | | template_value are updated to use DIRef. A paired commit at clang is required due to changes to DIBuilder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192320 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-c: Make target initializer functions external functions in lib.Anders Waldenborg2013-10-093-36/+55
| | | | | | | | | | | | | | | Making them proper functions defined in the (shared)lib instead of static inlines defined in the header files makes it possible to actually distribute a binary compiled against the shared library without having to worry about getting undefined symbol errors when calling e.g LLVMInitializeAllTargetInfos because the shared library on the other system was compiled with different targets. Differential Revision: http://llvm-reviews.chandlerc.com/D1714 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192316 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: In DIBuilder, the context field of a forward decl is updatedManman Ren2013-10-092-35/+47
| | | | | | | to use DIScopeRef. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192309 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing releases.Bill Wendling2013-10-091-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192304 91177308-0d34-0410-b5e6-96231b3b80d8
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