| Commit message (Collapse) | Author | Age | Files | Lines |
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CallOrPrologue correctly and eliminate the existing setter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132856 91177308-0d34-0410-b5e6-96231b3b80d8
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comment on their meaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132854 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132853 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132852 91177308-0d34-0410-b5e6-96231b3b80d8
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Thanks Bob Wilson for noticing it!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132851 91177308-0d34-0410-b5e6-96231b3b80d8
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Create a new CodeGenRegBank class that will eventually hold all the code
that computes the register structure from Records.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132849 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132844 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132839 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132836 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132834 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132830 91177308-0d34-0410-b5e6-96231b3b80d8
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creates loads like this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132826 91177308-0d34-0410-b5e6-96231b3b80d8
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and definitions when emitting global variables. This was causing global
declarations to be emitted as if they were definitions.
Fixes <rdar://problem/9429892>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132825 91177308-0d34-0410-b5e6-96231b3b80d8
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operand works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132824 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132822 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132821 91177308-0d34-0410-b5e6-96231b3b80d8
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With this I am able to bootstrap clang with early tail duplication enabled
for any small bb and setting tail-dup-size to a relatively large value(8) to
stress this code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132816 91177308-0d34-0410-b5e6-96231b3b80d8
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for structs like the given struct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132815 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132814 91177308-0d34-0410-b5e6-96231b3b80d8
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Prologue state,
causing an assertion failure downstream. This fixes <rdar://problem/9562908>.
This really seems like it should always be set at CCState creation time, so mistakes like
this can never happen. I'll take a look at doing that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132811 91177308-0d34-0410-b5e6-96231b3b80d8
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matches the ordering we prefer in instcombine. Part of rdar://9562809.
The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132809 91177308-0d34-0410-b5e6-96231b3b80d8
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eh edges. Swap the order of the checks to avoid it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132806 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132805 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132803 91177308-0d34-0410-b5e6-96231b3b80d8
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VK_PPC_{HA,LO}16 into darwin and gas variants.
Darwin wants {ha,lo}16(symbol) while gnu as wants symbol@{ha,l}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132802 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132800 91177308-0d34-0410-b5e6-96231b3b80d8
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pad, separating the exception and selector calls from the new lpad. Teaching
it not to do that, or to properly adjust the CFG afterwards, is out of
scope because it would require the other edges to the landing pad to be split
as well (effectively). Instead, just recover from the most likely cases
during inlining. The best long-term solution is to change the exception
representation and commit to either requiring or not requiring the more
complex edge-splitting logic; this is just a shorter-term hack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132799 91177308-0d34-0410-b5e6-96231b3b80d8
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No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132798 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132797 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132795 91177308-0d34-0410-b5e6-96231b3b80d8
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switch. (face+palm)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132790 91177308-0d34-0410-b5e6-96231b3b80d8
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do fast-isel, then try to fold instructions. PR10092.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132789 91177308-0d34-0410-b5e6-96231b3b80d8
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I'll be moving some more code there to gather all of the
register-specific stuff in one place. Currently it is shared between
CodeGenTarget and RegisterInfoEmitter.
The plan is that CodeGenRegisters can compute the full register bank
structure while RegisterInfoEmitter only will handle the printing part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132788 91177308-0d34-0410-b5e6-96231b3b80d8
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inline-asm-multichar.c test per this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132785 91177308-0d34-0410-b5e6-96231b3b80d8
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Radar 9558930.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132782 91177308-0d34-0410-b5e6-96231b3b80d8
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The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.
Some targets still use custom allocation orders:
ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.
X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.
SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132777 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132776 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132775 91177308-0d34-0410-b5e6-96231b3b80d8
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Patch by Pekka Jaaskelainen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132774 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132772 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132771 91177308-0d34-0410-b5e6-96231b3b80d8
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Patch by Jake Waskett!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132770 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132768 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132767 91177308-0d34-0410-b5e6-96231b3b80d8
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assuming that all offsets are legal vector accesses, and thus trying to access
the float member of { <2 x float>, float } as the 3rd element of the first
member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132766 91177308-0d34-0410-b5e6-96231b3b80d8
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of the frame then increase the maximum alignment of the frame to
match.
Fixes PR6965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132764 91177308-0d34-0410-b5e6-96231b3b80d8
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No functional change.
Part of PR6965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
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ConvertScalar_InsertValue. The
former was using the size of the entire alloca, whereas the latter was correctly using
the allocated size of the immediate type being converted (which may differ from the size
of the alloca). This fixes PR10082.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132759 91177308-0d34-0410-b5e6-96231b3b80d8
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dynamically allocated stack area was not set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132758 91177308-0d34-0410-b5e6-96231b3b80d8
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