aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Reserve number of MI operands to accom,odate complex patterns.Evan Cheng2012-03-201-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153125 91177308-0d34-0410-b5e6-96231b3b80d8
* remove unused variableMatt Beaumont-Gay2012-03-201-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153116 91177308-0d34-0410-b5e6-96231b3b80d8
* [avx] Add the AddedComplexity to the VINSERTI128 avx2 patterns to giveChad Rosier2012-03-201-1/+1
| | | | | | | precedence over the VINSERTF128 avx1 patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153114 91177308-0d34-0410-b5e6-96231b3b80d8
* Require a base pointer for stack realignment when SP may vary dynamically.Bob Wilson2012-03-201-2/+3
| | | | | | | | | | | | | ARMBaseRegisterInfo::canRealignStack was checking for variable-sized objects but not for stack adjustments around calls. Use hasReservedCallFrame() to check for both. The hasBasePointer function was already correctly checking both conditions, so the effect of this was that a base pointer would be used without checking whether the base pointer register could be reserved. I don't have a small testcase for this. <rdar://problem/11075906> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153110 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some redundant checks.Bob Wilson2012-03-202-3/+2
| | | | | | | ARMFrameLowering::hasReservedCallFrame is already checking for variable sized objects, so there's no point in checking it twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153109 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace.Chad Rosier2012-03-201-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153105 91177308-0d34-0410-b5e6-96231b3b80d8
* [avx] Move the vextractf128 patterns closer to the vextractf128 def. RemoveChad Rosier2012-03-202-29/+26
| | | | | | | | whitespace from test case. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153103 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix assembling ARM vst2 instructions with double-spaced registers.Kevin Enderby2012-03-203-1/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153099 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM non-scattered MachO relocations for movw/movt.Jim Grosbach2012-03-202-22/+81
| | | | | | | | Needed when building -mdynamic-no-pic code. rdar://10459256 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153097 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test.Chad Rosier2012-03-201-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153095 91177308-0d34-0410-b5e6-96231b3b80d8
* [avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads.Chad Rosier2012-03-202-3/+16
| | | | | | | | | | | | | | | | | This results in things such as vmovups 16(%rdi), %xmm0 vinsertf128 $1, %xmm0, %ymm0, %ymm0 to be combined to vinsertf128 $1, 16(%rdi), %ymm0, %ymm0 rdar://11076953 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153092 91177308-0d34-0410-b5e6-96231b3b80d8
* The ARM instructions that have an unpredictable behavior when the pc ↵Silviu Baranga2012-03-207-9/+27
| | | | | | register operand is given now fail with soft fail. Modified the regression tests to reflect this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
* test commitSilviu Baranga2012-03-201-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153086 91177308-0d34-0410-b5e6-96231b3b80d8
* Test Commit - add a newlineRichard Barton2012-03-201-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153083 91177308-0d34-0410-b5e6-96231b3b80d8
* It's possible to have a constant expression who's size is quite big (e.g.,Bill Wendling2012-03-202-11/+34
| | | | | | | | | | | | | | | i128). In that case, we may not be able to print out the MCExpr as an expression. For instance, we could have an MCExpr like this: 0xBEEF0000BEEF0000 | (0xBEEF0000BEEF0000 << 64) The MCExpr printer handles sizes up to 64-bits, but this expression would require 128-bits. In this situation, try to evaluate the constant expression and emit that as the value into 64-bit chunks. <rdar://problem/11070338> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153081 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove code that prevented lowering shuffles if they are used by load and ↵Craig Topper2012-03-201-92/+111
| | | | | | themselves used by a extract_vector_elt. This was done to allow the DAG combiner to collapse to a single element load. Unfortunately, sometimes the extract_vector_elt would disappear before DAG combine could do the transformation leaving a vector_shuffle that isel couldn't handle. New code lets the shuffle be converted to a target specific node, but then adds a combine routine that can convert target specific nodes back to vector_shuffles if the folding criteria are met. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153080 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor out target shuffle mask decoding from getShuffleScalarElt and use a ↵Craig Topper2012-03-204-96/+95
| | | | | | SmallVector of int instead of unsigned for shuffle mask in decode functions. Preparation for another change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153079 91177308-0d34-0410-b5e6-96231b3b80d8
* When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add ↵Craig Topper2012-03-201-0/+1
| | | | | | users of the final load to the worklist too. Needed by changes I'm preparing to make to X86 backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153078 91177308-0d34-0410-b5e6-96231b3b80d8
* Do everything up to generating code to try to get a register forEric Christopher2012-03-201-1/+6
| | | | | | | | | | a variable. The previous code would break the debug info changing code invariant. This will regress debug info for arguments where we elide the alloca created. Fixes rdar://11066468 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153074 91177308-0d34-0410-b5e6-96231b3b80d8
* Untabify.Eric Christopher2012-03-201-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153073 91177308-0d34-0410-b5e6-96231b3b80d8
* Add another debugging statement here.Eric Christopher2012-03-201-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153072 91177308-0d34-0410-b5e6-96231b3b80d8
* Use lookUpRegForValue here instead of duplicating the code.Eric Christopher2012-03-201-9/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153071 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix two bugpoint bugs:Chris Lattner2012-03-191-5/+7
| | | | | | | | | | | | | | 1) opt is not usually in the same path as the target program. Even for the bugpoint as a standalone app, it should be more portable to search in PATH, isn't it? 2) bugpoint driver accounts opt plugins, but does not list them in the final output command. Patch by Dmitry Mikushin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153066 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR12301 - llvm-bcanalyze should print to stdout, not stderr (except for ↵Chris Lattner2012-03-191-48/+48
| | | | | | errors). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153065 91177308-0d34-0410-b5e6-96231b3b80d8
* f16 FDIV can now be legalized by promoting to f32Pete Cooper2012-03-191-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153064 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a build failure with libc++Chris Lattner2012-03-191-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153063 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM branch relaxation for unconditional t1 branches.Jim Grosbach2012-03-191-0/+11
| | | | | | rdar://11059157 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153055 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly, accept optional '#' on lane index number.Jim Grosbach2012-03-191-0/+6
| | | | | | rdar://11057160 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153053 91177308-0d34-0410-b5e6-96231b3b80d8
* [Object/COFF]: Expose getSectionContents.Michael J. Spencer2012-03-192-10/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153051 91177308-0d34-0410-b5e6-96231b3b80d8
* [Object/COFF]: Expose getSectionName.Michael J. Spencer2012-03-193-19/+32
| | | | | | Also add some documentation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153050 91177308-0d34-0410-b5e6-96231b3b80d8
* Perform mul combine when multiplying wiht negative constants.Anton Korobeynikov2012-03-192-18/+90
| | | | | | | | Patch by Weiming Zhao! This fixes PR12212 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153049 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an option to the MI scheduler to cut off scheduling after a fixed number ofLang Hames2012-03-191-1/+19
| | | | | | | | instructions have been scheduled. Handy for tracking down scheduler bugs, or bugs exposed by scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153045 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] don't emit __asan_mapping_offset/__asan_mapping_scale by default -- ↵Kostya Serebryany2012-03-191-12/+17
| | | | | | they are currently used only for experiments git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153040 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/DebugInfo: Move two tests to DebugInfo/X86. They are X86-dependent.NAKAMURA Takumi2012-03-192-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153038 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix DAG combine which creates illegal vector shuffles. Patch by Heikki Kultala.Duncan Sands2012-03-191-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153035 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds X86 instruction itineraries for non-pseudo opcodes inPreston Gurd2012-03-194-52/+83
| | | | | | | | | | | | | X86InstrCompiler.td. It also adds –mcpu-generic to the legalize-shift-64.ll test so the test will pass if run on an Intel Atom CPU, which would otherwise produce an instruction schedule which differs from that which the test expects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153033 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a note for -ffast-math optimization of vector norm.Benjamin Kramer2012-03-191-0/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153031 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the formatting of this file more consistent, and fix the 80-columnsChandler Carruth2012-03-181-42/+42
| | | | | | | | | | | violations I introduced. Also sort some of the instructions to get a more consistent ordering. Suggestions on still better / more consistent formatting would be welcome. I'm actually tempted to use a macro to define all of the delegate methods... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153030 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach InstVisitor about the UnaryInstruction layer in the instructionChandler Carruth2012-03-181-8/+9
| | | | | | | type hierarchy. I wanted to use this for the inline cost rewrite, and found it was missing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153029 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor out the multiply analysis code in ComputeMaskedBits and apply it to theNick Lewycky2012-03-182-68/+150
| | | | | | | | | overflow checking multiply intrinsic as well. Add a test for this, updating the test from grep to FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153028 91177308-0d34-0410-b5e6-96231b3b80d8
* isCommutedMOVLMask should only look at 128-bit vectors to match isMOVLMask.Craig Topper2012-03-181-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153027 91177308-0d34-0410-b5e6-96231b3b80d8
* This clause (although matching parts of the implementation) can't be correct.Nick Lewycky2012-03-181-2/+1
| | | | | | | Thanks to Eli for noticing the discrepancy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153011 91177308-0d34-0410-b5e6-96231b3b80d8
* CriticalAntiDepBreaker: Replace a SmallSet of regs with a much denser BitVector.Benjamin Kramer2012-03-172-11/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152999 91177308-0d34-0410-b5e6-96231b3b80d8
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-1788-134/+102
| | | | | | some superfluous forward declarations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
* MachineInstr: Inline the fast path (non-bundle instruction) of hasProperty.Benjamin Kramer2012-03-172-7/+14
| | | | | | This is particularly helpful as both arguments tend to be constants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152991 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some copy and paste remnants of Cell and SPU in Hexagon files.Craig Topper2012-03-174-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152981 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo in file header.Craig Topper2012-03-171-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152980 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass TargetOptions to HexagonTargetMachine constructor by reference to match ↵Craig Topper2012-03-172-3/+4
| | | | | | other targets and the base class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152979 91177308-0d34-0410-b5e6-96231b3b80d8
* Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper2012-03-1718-29/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152978 91177308-0d34-0410-b5e6-96231b3b80d8
* MC asm parser macro argument count was wrong when empty.Jim Grosbach2012-03-172-0/+15
| | | | | | | | evaluated to '1' when the argument list was empty (should be '0'). rdar://11057257 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152967 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-01-11 07:14:15 +0000