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* [PowerPC] Support TLS variables in debug infoUlrich Weigand2013-07-024-3/+53
| | | | | | | | | | | This adds an implementation of getDebugThreadLocalSymbol for (64-bit) PowerPC. This needs to return a generic MCExpr since on ppc64, we need to add a bias of 0x8000 to the value returned by the R_PPC64_DTPREL64 relocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185461 91177308-0d34-0410-b5e6-96231b3b80d8
* [DebugInfo] Allow getDebugThreadLocalSymbol to return MCExprUlrich Weigand2013-07-025-7/+7
| | | | | | | | | | | | | This allows getDebugThreadLocalSymbol to return a generic MCExpr instead of just a MCSymbolRefExpr. This is in preparation for supporting debug info for TLS variables on PowerPC, where we need to describe the variable location using a more complex expression than just MCSymbolRefExpr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185460 91177308-0d34-0410-b5e6-96231b3b80d8
* [DebugInfo] Hold generic MCExpr in AddrPoolUlrich Weigand2013-07-022-9/+9
| | | | | | | | | | | | | This changes the AddrPool infrastructure to enable it to hold generic MCExpr expressions, not just MCSymbolRefExpr. This is in preparation for supporting debug info for TLS variables on PowerPC, where we need to describe the variable location using a more complex expression than just MCSymbolRefExpr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185459 91177308-0d34-0410-b5e6-96231b3b80d8
* [DebugInfo] Introduce DIEExpr variant of DIEValue to hold MCExpr valuesUlrich Weigand2013-07-025-21/+80
| | | | | | | | | | | | | | This partially reverts r185202 and restores DIELabel to hold plain MCSymbol references. Instead, we add a new subclass DIEExpr of DIEValue that can hold generic MCExpr references. This is in preparation for supporting debug info for TLS variables on PowerPC, where we need to describe the variable location using a more complex expression than just MCSymbolRefExpr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185458 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: cleanupManman Ren2013-07-022-6/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185456 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert (most of) r185393 and r185395.Jakob Stoklund Olesen2013-07-022-80/+82
| | | | | | | | | | | "Remove floating point computations form SpillPlacement.cpp." These commits caused test failures in lencod on clang-native-arm-lnt. I suspect these changes are only exposing an existing issue, but reverting anyway to keep the bots passing while we investigate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185447 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Avoid unused variable warnings in Release builds.Benjamin Kramer2013-07-021-6/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185445 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix -Wsign-compare warning and remove windows-style line endings introduced ↵David Blaikie2013-07-021-17/+17
| | | | | | by r185421 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185443 91177308-0d34-0410-b5e6-96231b3b80d8
* [APFloat] Swap an early out check so we do not dereference str.end().Michael Gottesman2013-07-021-1/+1
| | | | | | | Originally if D.firstSigDigit == str.end(), we will have already dereferenced D.firstSigDigit in the first predicate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185437 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove address spaces from MC.Rafael Espindola2013-07-0224-209/+153
| | | | | | | | This is dead code since PIC16 was removed in 2010. The result was an odd mix, where some parts would carefully pass it along and others would assert it was zero (most of the object streamer for example). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185436 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Use DSGFR over DSGR in more casesRichard Sandiford2013-07-026-6/+49
| | | | | | | | | | | Fixes some cases where we were using full 64-bit division for (sdiv i32, i32) and (sdiv i64, i32). The "32" in "SDIVREM32" just refers to the second operand. The first operand of all *DIVREM*s is a GR128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185435 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Use MVC to spill loads and storesRichard Sandiford2013-07-026-13/+582
| | | | | | | | | | | | | | | | | | | | | | Try to use MVC when spilling the destination of a simple load or the source of a simple store. As explained in the comment, this doesn't yet handle the case where the load or store location is also a frame index, since that could lead to two simultaneous scavenger spills, something the backend can't handle yet. spill-02.py tests that this restriction kicks in, but unfortunately I've not yet found a case that would fail without it. The volatile trick I used for other scavenger tests doesn't work here because we can't use MVC for volatile accesses anyway. I'm planning on relaxing the restriction later, hopefully with a test that does trigger the problem... Tests @f8 and @f9 also showed that L(G)RL and ST(G)RL were wrongly classified as SimpleBDX{Load,Store}. It wouldn't be easy to test for that bug separately, which is why I didn't split out the fix as a separate patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185434 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add the MVC instructionRichard Sandiford2013-07-0211-127/+325
| | | | | | | | | | This is the first use of D(L,B) addressing, which required a fair bit of surgery. For that reason, the patch just adds the instruction definition and the associated assembler and disassembler support. A later patch will actually make use of it for codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185433 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Fix instruction selection for zext, mkmsk instructions.Richard Osborne2013-07-024-2/+20
| | | | | | | | | | | r182680 replaced CountLeadingZeros_32 with a template function countLeadingZeros that relies on using the correct argument type to give the right result. The type passed in the XCore backend after this revision was incorrect in a couple of places. Patch by Robert Lytton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185430 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM EHABI compact model 1 and 2 without handlerdata.Logan Chien2013-07-022-4/+14
| | | | | | | | | | | | | | | | According to ARM EHABI section 9.2, if the __aeabi_unwind_cpp_pr1() or __aeabi_unwind_cpp_pr2() is used, then the handler data must be emitted after the unwind opcodes. The handler data consists of several words, and should be terminated by zero. In case that the .handlerdata directive is not specified by the programmer, we should emit zero to terminate the handler data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185422 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed alignment of code sections in the JIT mode. Added a test to the ↵Elena Demikhovsky2013-07-022-2/+30
| | | | | | JITMemoryManager. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185421 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombiner: fix use-counting issue when forming zextloadTim Northover2013-07-022-1/+17
| | | | | | | | | | DAGCombiner was counting all uses of a load node when considering whether it's worth combining into a zextload. Really, it wants to ignore the chain and just count real uses. rdar://problem/13896307 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185419 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r185257 (InstCombine: Be more agressive optimizing 'udiv' instrs with ↵Hal Finkel2013-07-023-77/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'select' denoms) I'm reverting this commit because: 1. As discussed during review, it needs to be rewritten (to avoid creating and then deleting instructions). 2. This is causing optimizer crashes. Specifically, I'm seeing things like this: While deleting: i1 % Use still stuck around after Def is destroyed: <badref> = select i1 <badref>, i32 0, i32 1 opt: /src/llvm-trunk/lib/IR/Value.cpp:79: virtual llvm::Value::~Value(): Assertion `use_empty() && "Uses remain when a value is destroyed!"' failed. I'd guess that these will go away once we're no longer creating/deleting instructions here, but just in case, I'm adding a regression test. Because the code is bring rewritten, I've just XFAIL'd the original regression test. Original commit message: InstCombine: Be more agressive optimizing 'udiv' instrs with 'select' denoms Real world code sometimes has the denominator of a 'udiv' be a 'select'. LLVM can handle such cases but only when the 'select' operands are symmetric in structure (both select operands are a constant power of two or a left shift, etc.). This falls apart if we are dealt a 'udiv' where the code is not symetric or if the select operands lead us to more select instructions. Instead, we should treat the LHS and each select operand as a distinct divide operation and try to optimize them independently. If we can to simplify each operation, then we can replace the 'udiv' with, say, a 'lshr' that has a new select with a bunch of new operands for the select. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185415 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing break statements. Noticed by inspection.Nick Lewycky2013-07-021-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185414 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo in commentTobias Grosser2013-07-021-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185413 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handlingHal Finkel2013-07-026-35/+331
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a couple of (small) related changes here: 1. The printed name of the VRSAVE register has been changed from VRsave to vrsave in order to match the name accepted by GNU binutils. 2. Support for parsing vrsave has been added to the asm parser (it seems that there was no test case specifically covering this code, so I've added one). 3. The list of Altivec registers, which was common to all calling conventions, has been separated out. This allows us to define the base CSR lists, and then lists for each ABI with Altivec included. This allows SjLj, for example, to work correctly on non-Altivec targets without using unnatural definitions of the NoRegs CSR list. 4. VRSAVE is now always reserved on non-Darwin targets and all Altivec registers are reserved when Altivec is disabled. With these changes, it is now possible to compile a function containing __builtin_unwind_init() on Linux/PPC64 with debugging information. This did not work previously because GNU binutils assumes that all .cfi_offset offsets will be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned offset). This is not true for the vrsave register, however, because this register is used only on Darwin, GCC does not bother printing a .cfi_offset entry for it (even though there is a slot in the stack frame for it as specified by the ABI). This change allows us to do the same: we will also not print .cfi_offset directives for vrsave. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185409 91177308-0d34-0410-b5e6-96231b3b80d8
* IRVerifier: Correctly check attribute typesTobias Grosser2013-07-021-1/+2
| | | | | | | | | | | Add missing parenthesis such that all and not only the very first attribute is checked. Testing this piece of code is not possible with an LLVM-IR test file, as the LLVM-IR parser has a similar check such that the wrong IR does not even arrive at the verifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185408 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add new InstrItinClasses for move from/to coprocessor instructions andAkira Hatanaka2013-07-024-56/+70
| | | | | | | | | floating point loads and stores. No changes in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185399 91177308-0d34-0410-b5e6-96231b3b80d8
* PR14728: DebugInfo: TLS variables with -gsplit-dwarfDavid Blaikie2013-07-014-17/+57
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185398 91177308-0d34-0410-b5e6-96231b3b80d8
* [APFloat] Ensure that we can properly parse strings that do not have null ↵Michael Gottesman2013-07-012-1/+33
| | | | | | | | terminators. rdar://14323230 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185397 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix up some asserts that are within an if statement. This removes the needRichard Trieu2013-07-011-4/+6
| | | | | | | for assert(0 && "text"). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185396 91177308-0d34-0410-b5e6-96231b3b80d8
* Tweak some comments that referred to the old bias computations.Jakob Stoklund Olesen2013-07-011-13/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185395 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add support for TLS data relocationsUlrich Weigand2013-07-017-2/+45
| | | | | | | | | | | | This adds support for TLS data relocations and modifiers: .quad target@dtpmod .quad target@tprel .quad target@dtprel Currently exploited by the asm parser only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185394 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove floating point computations form SpillPlacement.cpp.Jakob Stoklund Olesen2013-07-013-69/+70
| | | | | | | | | | | | | | | | | | Patch by Benjamin Kramer! Use the BlockFrequency class instead of floats in the Hopfield network computations. This rescales the node Bias field from a [-2;2] float range to two block frequencies BiasN and BiasP pulling in opposite directions. This construct has a more predictable behavior when block frequencies saturate. The per-node scaling factors are no longer necessary, assuming the block frequencies around a bundle are consistent. This patch can cause the register allocator to make different spilling decisions. The differences should be small. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185393 91177308-0d34-0410-b5e6-96231b3b80d8
* Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ...Richard Trieu2013-07-011-7/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185392 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Fix 32-bit PowerPC TLS relocsUlrich Weigand2013-07-012-8/+14
| | | | | | | | | Some TLS relocs were copied incorrectly from ppc64 to ppc32, and some were missing completely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185390 91177308-0d34-0410-b5e6-96231b3b80d8
* PR16493: DebugInfo with TLS on PPC crashing due to invalid relocationDavid Blaikie2013-07-017-9/+38
| | | | | | | | Restrict the current TLS support to X86 ELF for now. Test that we don't produce it on PPC & we can flesh that test case out with the right thing once someone implements it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185389 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support all condition register logical instructionsUlrich Weigand2013-07-013-12/+54
| | | | | | | | | This adds support for all missing condition register logical instructions and extended mnemonics to the asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185387 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a newline.Chad Rosier2013-07-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185385 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: clean up usage of Verify.Manman Ren2013-07-012-17/+19
| | | | | | | | No functionality change. It should suffice to check the type of a debug info metadata, instead of calling Verify. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185383 91177308-0d34-0410-b5e6-96231b3b80d8
* Index: test/CodeGen/PowerPC/reloc-align.llBill Schmidt2013-07-013-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | =================================================================== --- test/CodeGen/PowerPC/reloc-align.ll (revision 0) +++ test/CodeGen/PowerPC/reloc-align.ll (revision 0) @@ -0,0 +1,34 @@ +; RUN: llc -mcpu=pwr7 -O1 < %s | FileCheck %s + +; This test verifies that the peephole optimization of address accesses +; does not produce a load or store with a relocation that can't be +; satisfied for a given instruction encoding. Reduced from a test supplied +; by Hal Finkel. + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.S1 = type { [8 x i8] } + +@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1 + +; Function Attrs: nounwind readonly +define signext i32 @main() #0 { +entry: + %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*)) +; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l + ret i32 %call +} + +; Function Attrs: nounwind readonly +define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 { +entry: + %0 = bitcast %struct.S1* %p_91 to i64* + %bf.load = load i64* %0, align 1 + %bf.shl = shl i64 %bf.load, 26 + %bf.ashr = ashr i64 %bf.shl, 54 + %bf.cast = trunc i64 %bf.ashr to i32 + ret i32 %bf.cast +} + +attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } Index: lib/Target/PowerPC/PPCAsmPrinter.cpp =================================================================== --- lib/Target/PowerPC/PPCAsmPrinter.cpp (revision 185327) +++ lib/Target/PowerPC/PPCAsmPrinter.cpp (working copy) @@ -679,7 +679,26 @@ void PPCAsmPrinter::EmitInstruction(const MachineI OutStreamer.EmitRawText(StringRef("\tmsync")); return; } + break; + case PPC::LD: + case PPC::STD: + case PPC::LWA: { + // Verify alignment is legal, so we don't create relocations + // that can't be supported. + // FIXME: This test is currently disabled for Darwin. The test + // suite shows a handful of test cases that fail this check for + // Darwin. Those need to be investigated before this sanity test + // can be enabled for those subtargets. + if (!Subtarget.isDarwin()) { + unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1; + const MachineOperand &MO = MI->getOperand(OpNum); + if (MO.isGlobal() && MO.getGlobal()->getAlignment() < 4) + llvm_unreachable("Global must be word-aligned for LD, STD, LWA!"); + } + // Now process the instruction normally. + break; } + } LowerPPCMachineInstrToMCInst(MI, TmpInst, *this); OutStreamer.EmitInstruction(TmpInst); Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp =================================================================== --- lib/Target/PowerPC/PPCISelDAGToDAG.cpp (revision 185327) +++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp (working copy) @@ -1530,6 +1530,14 @@ void PPCDAGToDAGISel::PostprocessISelDAG() { if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) { SDLoc dl(GA); const GlobalValue *GV = GA->getGlobal(); + // We can't perform this optimization for data whose alignment + // is insufficient for the instruction encoding. + if (GV->getAlignment() < 4 && + (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD || + StorageOpcode == PPC::LWA)) { + DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n"); + continue; + } ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags); } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(ImmOpnd)) { git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185380 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMAsmParser] Sort the ARM register lists based on the encoding value, not theChad Rosier2013-07-013-36/+44
| | | | | | | tablegen enum values. This should be the last fix due to fallout from r185094. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185379 91177308-0d34-0410-b5e6-96231b3b80d8
* Make PBQP require/preserve MachineLoopInfo - the spiller requires it.Lang Hames2013-07-011-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185378 91177308-0d34-0410-b5e6-96231b3b80d8
* [docs] Amend confusing titleSean Silva2013-07-011-3/+3
| | | | | | | | | | "Writing an LLVM Compiler Backend" can be misinterpreted as meaning "backend" in the sense of "using LLVM as a backend for your compiler for your new language". This new name is less ambiguous. As a bonus, this brings the title in line with the file name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185377 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Reverse the order of source operands of shift and rotate instructions ↵Akira Hatanaka2013-07-012-8/+8
| | | | | | | | | | | that have three register operands. No intended functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185376 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Also add "msync" aliasUlrich Weigand2013-07-012-0/+3
| | | | | | | | | This adds an alias for "msync" (which is used on Book E systems instead of "sync"). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185375 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Increase the number of floating point control registers available to 32.Akira Hatanaka2013-07-015-20/+25
| | | | | | | | | Create a dedicated register class for floating point condition code registers and move FCC0 from register class CCR to the new register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix test case to check that mips64 instructions are generated.Akira Hatanaka2013-07-011-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185371 91177308-0d34-0410-b5e6-96231b3b80d8
* Really fix the test. Sorry for the breakage...Anton Korobeynikov2013-07-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185369 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the test which relies on uncommitted changeAnton Korobeynikov2013-07-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185368 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the build after r185363. Use llvm::next instead of raw next.Cameron Zwarich2013-07-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185367 91177308-0d34-0410-b5e6-96231b3b80d8
* Add jump tables handling for MSP430.Anton Korobeynikov2013-07-013-0/+65
| | | | | | | Patch by Job Noorman! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185364 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR16508.Cameron Zwarich2013-07-012-4/+36
| | | | | | | | | | | | When phis get lowered, destination copies are inserted using an iterator that is determined once for all phis in the block, which BuildMI interprets as a request to insert an instruction directly before the iterator. In the case of a cyclic phi, source copies may also be inserted directly before this iterator, which can cause source copies to be inserted before destination copies. The fix is to keep an iterator to the last phi and then advance it while lowering each phi in order to insert destination copies directly after the phis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185363 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't form PPC CTR loops for over-sized exit countsHal Finkel2013-07-012-0/+26
| | | | | | | | | | Although you can't generate this from C on PPC64, if you have a loop using a 64-bit counter on PPC32 then you can't form a CTR-based loop for it. This had been cauing the PPCCTRLoops pass to assert. Thanks to Joerg Sonnenberger for providing a test case! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185361 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: correct CodeGen of MOVZ/MOVK combinations.Tim Northover2013-07-014-17/+36
| | | | | | | | | | | | According to the AArch64 ELF specification (4.6.8), it's the assembler's responsibility to make sure the shift amount is correct in relocated MOVZ/MOVK instructions. This wasn't being obeyed by either the MCJIT CodeGen or RuntimeDyldELF (which happened to work out well for JIT tests). This commit should make us compliant in this area. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185360 91177308-0d34-0410-b5e6-96231b3b80d8
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