aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* TargetLowering: Use the large shift amount during legalize types. The ↵Benjamin Kramer2012-08-172-3/+35
| | | | | | legalizer may call us with an overly large type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162101 91177308-0d34-0410-b5e6-96231b3b80d8
* Use standard pattern for iterate+erase.Jakob Stoklund Olesen2012-08-171-9/+2
| | | | | | | | | Increment the MBB iterator at the top of the loop to properly handle the current (and previous) instructions getting erased. This fixes PR13625. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162099 91177308-0d34-0410-b5e6-96231b3b80d8
* Guard MemoryBuiltins against self-looping GEPs, which can occur in ↵Benjamin Kramer2012-08-172-0/+21
| | | | | | | | unreachable code due to constant propagation. Fixes PR13621. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162098 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix broken check lines.Benjamin Kramer2012-08-1710-28/+27
| | | | | | | | I really need to find a way to automate this, but I can't come up with a regex that has no false positives while handling tricky cases like custom check prefixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162097 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement NEON domain switching for scalar <-> S-register vmovs on ARMTim Northover2012-08-172-47/+129
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162094 91177308-0d34-0410-b5e6-96231b3b80d8
* Insertion of NoFolder functions to avoid ambiguous overload warnings or ↵Jin-Gu Kang2012-08-171-0/+12
| | | | | | errors about whether to convert Idx to ArrayRef<Constant *> or ArrayRef<Value *> like ConstantFolder and TargetFolder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162090 91177308-0d34-0410-b5e6-96231b3b80d8
* Use nested switch to select arguments to reduce calls to EmitPCMP.Craig Topper2012-08-171-5/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162089 91177308-0d34-0410-b5e6-96231b3b80d8
* Make ReplaceATOMIC_BINARY_64 a static function. Use a nested switch to ↵Craig Topper2012-08-172-19/+30
| | | | | | reduce to only a single call to it thus allowing it to be inlined by the compiler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162088 91177308-0d34-0410-b5e6-96231b3b80d8
* Test commit.Pranav Bhandarkar2012-08-171-1/+1
| | | | | | | | include/llvm/IntrinsicsHexagon.td: Hexagon_Intrinsic is the base class for all Hexagon intrinsics and not altivec intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162087 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary include of ARMGenInstrInfo.inc.Craig Topper2012-08-171-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162086 91177308-0d34-0410-b5e6-96231b3b80d8
* Declare some for loop indices inside the for loop statement.Craig Topper2012-08-171-20/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162085 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix up indentation of outputted decode function for readability.Craig Topper2012-08-171-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162082 91177308-0d34-0410-b5e6-96231b3b80d8
* lit: Show actually created count of threads. The incorrect threads count is ↵NAKAMURA Takumi2012-08-171-3/+3
| | | | | | | | printed if the number of tests are less than the number of default threads. Thanks to Vinson Lee, reported in PR13620. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162078 91177308-0d34-0410-b5e6-96231b3b80d8
* Flatten the aligned-char-array utility template to be a directlyChandler Carruth2012-08-173-134/+133
| | | | | | | templated union at the request of Richard Smith. This makes it substantially easier to type. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162072 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ADD and SUB to the predicable ARM instructions.Jakob Stoklund Olesen2012-08-166-21/+86
| | | | | | | | | | It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162061 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle ARM MOVCC optimization in PeepholeOptimizer.Jakob Stoklund Olesen2012-08-165-53/+73
| | | | | | Use the target independent select analysis hooks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162060 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an MCID::Select flag and TII hooks for optimizing selects.Jakob Stoklund Olesen2012-08-168-16/+89
| | | | | | | | | | | | Select instructions pick one of two virtual registers based on a condition, like x86 cmov. On targets like ARM that support predication, selects can sometimes be eliminated by predicating the instruction defining one of the operands. Teach PeepholeOptimizer to recognize select instructions, and ask the target to optimize them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162059 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r162034, r162035 and r162037.Roman Divacky2012-08-164-44/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162039 91177308-0d34-0410-b5e6-96231b3b80d8
* Define and handle additional fixup kinds. By Adhemerval Zanella.Roman Divacky2012-08-162-1/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162037 91177308-0d34-0410-b5e6-96231b3b80d8
* Add PPC64 relocations definitions, by Adhemerval Zanella.Roman Divacky2012-08-161-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162035 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle PowerPC.Roman Divacky2012-08-161-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162034 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo and grammar. By Adhemerval Zanella.Roman Divacky2012-08-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162032 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach GVN to reason about edges dominating uses. This allows it to handle casesRafael Espindola2012-08-164-62/+133
| | | | | | | | | | | | | where some fact lake a=b dominates a use in a phi, but doesn't dominate the basic block itself. This feature could also be implemented by splitting critical edges, but at least with the current algorithm reasoning about the dominance directly is faster. The time for running "opt -O2" in the testcase in pr10584 is 1.003 times slower and on gcc as a single file it is 1.0007 times faster. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162023 91177308-0d34-0410-b5e6-96231b3b80d8
* Add dump/dumpr methods to SDValue.Nadav Rotem2012-08-161-2/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162014 91177308-0d34-0410-b5e6-96231b3b80d8
* [arm-fast-isel] Add support for fastcc.Jush Lu2012-08-162-3/+72
| | | | | | | | | Without fastcc support, the caller just falls through to CallingConv::C for fastcc, but callee still uses fastcc, this inconsistency of calling convention is a problem, and fastcc support can fix it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162013 91177308-0d34-0410-b5e6-96231b3b80d8
* Patch to enable FMA on bdver2 target. Make XOP feature enable FMA4 as well.Anitha Boyapati2012-08-161-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162012 91177308-0d34-0410-b5e6-96231b3b80d8
* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162010 ↵Anitha Boyapati2012-08-161-2/+2
| | | | 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r162008.Akira Hatanaka2012-08-161-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162009 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Android ABI to Mips backend to handle functions returning vectors of fourAkira Hatanaka2012-08-163-0/+18
| | | | | | | | | floats. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162008 91177308-0d34-0410-b5e6-96231b3b80d8
* bug in experimental targetsVictor Oliveira2012-08-151-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161995 91177308-0d34-0410-b5e6-96231b3b80d8
* Fold predicable instructions into MOVCC / t2MOVCC.Jakob Stoklund Olesen2012-08-157-3/+165
| | | | | | | | | | | | | | The ARM select instructions are just predicated moves. If the select is the only use of an operand, the instruction defining the operand can be predicated instead, saving one instruction and decreasing register pressure. This implementation can turn AND/ORR/EOR instructions into their corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to predicate any instruction, but we don't yet support predicated instructions in SSA form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161994 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead flag.Bill Wendling2012-08-151-9/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161990 91177308-0d34-0410-b5e6-96231b3b80d8
* Rework test so that it reproduces the error without the horrible flag.Bill Wendling2012-08-151-8/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161989 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove invalid test. This test requires that dead basic blocks be keptBill Wendling2012-08-151-19/+0
| | | | | | | | | | | | | | | | | around. That's not how we do things. Besides, the commit message tells us that it is covered by the GCC test suite. ------------------------------------------------------------------------ r127497 | zwarich | 2011-03-11 13:51:56 -0800 (Fri, 11 Mar 2011) | 3 lines Fix the GCC test suite issue exposed by r127477, which was caused by stack protector insertion not working correctly with unreachable code. Since that revision was rolled out, this test doesn't actual fail before this fix. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161985 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a problem in the JIT memory allocator whereSean Callanan2012-08-151-0/+3
| | | | | | | | | | | allocations of executable memory would not be padded to account for the size of the allocation header. This resulted in undersized allocations, meaning that when the allocation was written to later the next allocation's header would be corrupted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161984 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a CoveringSubRegIndices field to SubRegIndex records.Jakob Stoklund Olesen2012-08-152-9/+40
| | | | | | | This can be used to tell TableGen to use a specific SubRegIndex instead of synthesizing one when discovering all sub-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161982 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly test the LLVM_USE_RVALUE_REFERENCES macro.Michael J. Spencer2012-08-151-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161979 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly test the LLVM_USE_RVALUE_REFERENCES macro.Michael J. Spencer2012-08-153-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161978 91177308-0d34-0410-b5e6-96231b3b80d8
* [PathV2] Add mapped_file_region. Implementation for Windows and POSIX.Michael J. Spencer2012-08-154-26/+421
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161976 91177308-0d34-0410-b5e6-96231b3b80d8
* Add LLVM_DELETED_FUNCTION compatibility macro.Michael J. Spencer2012-08-151-0/+19
| | | | | | | | | | | | This should replace uses of: class A { A(const &A); // DO NOT IMPLEMENT public: ... }; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161975 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo in VariadicFunction.h that leads to invalid code in macro expansion.Chad Rosier2012-08-151-1/+1
| | | | | | Patch by Andy Gibbs <andyg1001@hotmail.co.uk> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161973 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix another roundToIntegral bug where very large values could become ↵Owen Anderson2012-08-152-1/+20
| | | | | | infinity. Problem and solution identified by Steve Canon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161969 91177308-0d34-0410-b5e6-96231b3b80d8
* Make synthesized sub-register indexes available in the target namespace.Jakob Stoklund Olesen2012-08-153-33/+30
| | | | | | | | | | | TableGen sometimes synthesizes missing sub-register indexes. Emit these indexes as enumerators in the target namespace along with the user-defined ones. Also take this opportunity to stop creating new Record objects for synthetic indexes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161964 91177308-0d34-0410-b5e6-96231b3b80d8
* Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows ↵Evan Cheng2012-08-155-19/+99
| | | | | | unaligned access. rdar://12091029 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161962 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo in comment.Owen Anderson2012-08-151-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161956 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing Rfalse operand to the predicated pseudo-instructions.Jakob Stoklund Olesen2012-08-153-28/+41
| | | | | | | | | | | | | | | | | | | | | | | When predicating this instruction: Rd = ADD Rn, Rm We need an extra operand to represent the value given to Rd when the predicate is false: Rd = ADDCC Rfalse, Rn, Rm, pred The Rd and Rfalse operands are different registers while in SSA form. Rfalse is tied to Rd to make sure they get the same register during register allocation. Previously, Rd and Rn were tied, but that is not required. Compare to MOVCC: Rd = MOVCC Rfalse, Rtrue, pred git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161955 91177308-0d34-0410-b5e6-96231b3b80d8
* Set the branch probability of branching to the 'normal' destination of an invokeBill Wendling2012-08-152-2/+31
| | | | | | | | | | | instruction to something absurdly high, while setting the probability of branching to the 'unwind' destination to the bare minimum. This should set cause the normal destination's invoke blocks to be moved closer to the invoke. PR13612 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161944 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a const violation in the generated disassembler.Benjamin Kramer2012-08-151-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161940 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] implement --asan-always-slow-path, which is a part of the improvement ↵Kostya Serebryany2012-08-151-2/+5
| | | | | | to handle unaligned partially OOB accesses. See http://code.google.com/p/address-sanitizer/issues/detail?id=100 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161937 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a problem with APFloat::roundToIntegral where it would return incorrect ↵Owen Anderson2012-08-152-0/+42
| | | | | | results for negative inputs to trunc. Add unit tests to verify this behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161929 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-08-04 23:34:00 +0000