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* Remove the LLVMContext& arguments from *Folder constructors, as they don't ↵Frits van Bommel2011-04-033-10/+6
| | | | | | seem to be used anywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128793 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typos on LLVM.cmake. Export LLVM_ON_UNIX & LLVM_ON_WIN32.Oscar Fuentes2011-04-031-3/+3
| | | | | | Patch by arrowdodger! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128789 91177308-0d34-0410-b5e6-96231b3b80d8
* PR9446: RecursivelyDeleteTriviallyDeadInstructions can delete the instructionEli Friedman2011-04-023-5/+36
| | | | | | | | | | | | | after the given instruction; make sure to handle that case correctly. (It's difficult to trigger; the included testcase involves a dead block, but I don't think that's a requirement.) While I'm here, get rid of the unnecessary warning about SimplifyInstructionsInBlock, since it should work correctly as far as I know. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128782 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't assume something which might be a constant expression is an instruction.Eli Friedman2011-04-021-3/+3
| | | | | | | | | Based on PR9429, but no testcase because I can't figure out how to trigger it anymore given other changes to the relevant code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128781 91177308-0d34-0410-b5e6-96231b3b80d8
* While SimplifyDemandedBits constant folds this, we can't rely on it here.Benjamin Kramer2011-04-021-2/+7
| | | | | | | | | | It's possible to craft an input that hits the recursion limits in a way that SimplifyDemandedBits doesn't simplify the icmp but ComputeMaskedBits can infer which bits are zero. No test case as it depends on too many other things. Fixes PR9609. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128777 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle changing of LLVM_ENABLE_FFI.Oscar Fuentes2011-04-021-0/+4
| | | | | | | | | | | | | | If someone first configure build with LLVM_ENABLE_FFI=1 and then turn it off, the build will fail in lib/ExecutionEngine/Interpreter because Interpreter will try still to #include <ffi/ffi.h>, but there are no include_directories(${FFI_INCLUDE_DIR}) now. This patch unset()'s HAVE_FFI_H and HAVE_FFI_FFI_H from cache file if LLVM_ENABLE_FFI=0. This forces CMake to update config.h. Patch by arrowdodger! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128769 91177308-0d34-0410-b5e6-96231b3b80d8
* ptx: support setp's 4-operand formatChe-Liang Chiou2011-04-023-35/+111
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128767 91177308-0d34-0410-b5e6-96231b3b80d8
* Use InterferenceCache in RegAllocGreedy.Jakob Stoklund Olesen2011-04-021-94/+46
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128765 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an InterferenceCache class for caching per-block interference ranges.Jakob Stoklund Olesen2011-04-025-1/+304
| | | | | | | | When the greedy register allocator is splitting multiple global live ranges, it tends to look at the same interference data many times. The InterferenceCache class caches queries for unaltered LiveIntervalUnions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128764 91177308-0d34-0410-b5e6-96231b3b80d8
* Use basic block numbers as indexes when mapping slot index ranges.Jakob Stoklund Olesen2011-04-022-41/+28
| | | | | | This is more compact and faster than using DenseMap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128763 91177308-0d34-0410-b5e6-96231b3b80d8
* Do some peephole optimizations to remove pointless VMOVs from Neon to integerCameron Zwarich2011-04-022-0/+42
| | | | | | | | registers that arise from argument shuffling with the soft float ABI. These instructions are particularly slow on Cortex A8. This fixes one half of <rdar://problem/8674845>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128759 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a RemoveFromWorklist method to DCI. This is needed to do some complicatedCameron Zwarich2011-04-022-0/+5
| | | | | | | | transformations in target-specific DAG combines without causing DAGCombiner to delete the same node twice. If you know of a better way to avoid this (see my next patch for an example), please let me know. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128758 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug in disassembly of STR_POST, where the immediate is the second ↵Johnny Chen2011-04-022-5/+16
| | | | | | | | | | | operand in am2offset; instead of the second operand in addrmode_imm12. rdar://problem/9225289 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128757 91177308-0d34-0410-b5e6-96231b3b80d8
* Undo changes mistakenly made in revision 128750.Akira Hatanaka2011-04-022-27/+59
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128751 91177308-0d34-0410-b5e6-96231b3b80d8
* Insert space before ';' to prevent warnings.Akira Hatanaka2011-04-023-60/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128750 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.Johnny Chen2011-04-012-0/+14
| | | | | | | rdar://problem/9224276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128749 91177308-0d34-0410-b5e6-96231b3b80d8
* MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is ↵Johnny Chen2011-04-012-0/+18
| | | | | | | | | UNPREDICTABLE. rdar://problem/9224120 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128748 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the instruction table entries for AI1_adde_sube_s_irs multiclass ↵Johnny Chen2011-04-012-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | definition so that all the instruction have: let Inst{31-27} = 0b1110; // non-predicated Before, the ARM decoder was confusing: > 0x40 0xf3 0xb8 0x80 as: Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcs pc, r8, r0, asr #6 since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'. Now, the AR decoder behaves correctly: > 0x40 0xf3 0xb8 0x80 > END Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcshi pc, r8, r0, asr #6 > rdar://problem/9223094 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128746 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment.Benjamin Kramer2011-04-011-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128745 91177308-0d34-0410-b5e6-96231b3b80d8
* Tweaks to the icmp+sext-to-shifts optimization to address Frits' comments:Benjamin Kramer2011-04-011-6/+6
| | | | | | | | | | - Localize the check if an icmp has one use to a place where we know we're introducing something that's likely more expensive than a sext from i1. - Add an assert to make sure a case that would lead to a miscompilation is folded away earlier. - Fix a typo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128744 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid de-referencing pass beginning of a basic block. No small test case ↵Evan Cheng2011-04-011-18/+21
| | | | | | possible. rdar://9216009 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128743 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove redundant code. There are assignments to variables Base and Offset ↵Akira Hatanaka2011-04-011-5/+0
| | | | | | right after the code that is removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128742 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplifies logic for printing target flags.Akira Hatanaka2011-04-013-34/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128741 91177308-0d34-0410-b5e6-96231b3b80d8
* CMake: remove debug code from previous commit.Oscar Fuentes2011-04-011-4/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128740 91177308-0d34-0410-b5e6-96231b3b80d8
* When the architecture is explicitly armv6 or thumbv6, we need to mark the ↵Owen Anderson2011-04-011-9/+15
| | | | | | object file appropriately. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128739 91177308-0d34-0410-b5e6-96231b3b80d8
* LDRD/STRD instructions should print both Rt and Rt2 in the asm string.Jim Grosbach2011-04-013-12/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128736 91177308-0d34-0410-b5e6-96231b3b80d8
* tlbgen/MC: StringRef's to temporary objects considered harmful.Daniel Dunbar2011-04-011-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128735 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we ↵Johnny Chen2011-04-013-0/+23
| | | | | | | | | should reject the instruction as invalid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128734 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix build.Benjamin Kramer2011-04-011-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128733 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Turn icmp + sext into bitwise/integer ops when the input has ↵Benjamin Kramer2011-04-012-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | only one unknown bit. int test1(unsigned x) { return (x&8) ? 0 : -1; } int test3(unsigned x) { return (x&8) ? -1 : 0; } before (x86_64): _test1: andl $8, %edi cmpl $1, %edi sbbl %eax, %eax ret _test3: andl $8, %edi cmpl $1, %edi sbbl %eax, %eax notl %eax ret after: _test1: shrl $3, %edi andl $1, %edi leal -1(%rdi), %eax ret _test3: shll $28, %edi movl %edi, %eax sarl $31, %eax ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128732 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Move (sext icmp) transforms into their own method. No intended ↵Benjamin Kramer2011-04-012-37/+43
| | | | | | functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128731 91177308-0d34-0410-b5e6-96231b3b80d8
* Add comments.Evan Cheng2011-04-011-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128730 91177308-0d34-0410-b5e6-96231b3b80d8
* Assign node order numbers to results of call instruction lowering. This ↵Evan Cheng2011-04-011-4/+8
| | | | | | should improve src line debug info when sdisel is used. rdar://9199118 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128728 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix assignment of -fPIC to CMAKE_C_FLAGS. Configure llvm-config.in.inOscar Fuentes2011-04-012-5/+9
| | | | | | | | | with the contents of CMAKE_C(XX)_FLAGS too, else `llvm-config --c(xx)flags' doesn't tell the absolute truth. This comes from PR9603 and is based on a patch by Ryuta Suzuki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128727 91177308-0d34-0410-b5e6-96231b3b80d8
* Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it ↵Akira Hatanaka2011-04-011-1/+26
| | | | | | handles delay slots correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128724 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix LDRi12 immediate operand, which was changed to be the second operand in ↵Johnny Chen2011-04-012-3/+13
| | | | | | | | | $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). rdar://problem/9219356 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128722 91177308-0d34-0410-b5e6-96231b3b80d8
* Update CMakeLists.txtDevang Patel2011-04-011-1/+1
| | | | | | | | Patch by arrowdoger. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128719 91177308-0d34-0410-b5e6-96231b3b80d8
* Add code for analyzing FP branches. Clean up branch Analysis functions.Akira Hatanaka2011-04-014-225/+186
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128718 91177308-0d34-0410-b5e6-96231b3b80d8
* Initialize HasVMLxForwarding.Benjamin Kramer2011-04-011-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128709 91177308-0d34-0410-b5e6-96231b3b80d8
* Various Instructions' resizeOperands() methods are only used to grow theJay Foad2011-04-012-58/+20
| | | | | | list of operands. Simplify and rename them accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128708 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test case.Evan Cheng2011-04-011-0/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128707 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheck'ify test.Evan Cheng2011-04-011-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128706 91177308-0d34-0410-b5e6-96231b3b80d8
* While testing dragonegg I noticed that isCastable and getCastOpcodeDuncan Sands2011-04-012-4/+25
| | | | | | | | | had gotten out of sync: isCastable didn't think it was possible to cast the x86_mmx type to anything, while it did think it possible to cast an i64 to x86_mmx. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128705 91177308-0d34-0410-b5e6-96231b3b80d8
* Add annotations to tablegen-generated processor itineraries, or replace them ↵Andrew Trick2011-04-012-16/+21
| | | | | | with something meaningful. I want to be able to read and debug the generated tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128703 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2011-04-012-68/+68
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128701 91177308-0d34-0410-b5e6-96231b3b80d8
* Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.Evan Cheng2011-04-014-19/+174
| | | | | | | rdar://8911343 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128696 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused variablesMatt Beaumont-Gay2011-04-011-3/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128692 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Thumb and Thumb2 tests to be register allocator independent.Jakob Stoklund Olesen2011-03-315-23/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128690 91177308-0d34-0410-b5e6-96231b3b80d8
* Apply again changes to support ARM memory asm parsing. I removedBruno Cardoso Lopes2011-03-3110-76/+363
| | | | | | | | | | | | | | all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
* The basic register allocator must also use the inline spiller.Jakob Stoklund Olesen2011-03-311-1/+1
| | | | | | | It is using a trivial rewriter that doesn't know how to insert spill code requested by the standard spiller. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128688 91177308-0d34-0410-b5e6-96231b3b80d8
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