| Commit message (Collapse) | Author | Age | Files | Lines |
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U lib/MC/MCSectionCOFF.cpp
U lib/CodeGen/TargetLoweringObjectFileImpl.cpp
U test/MC/COFF/weak-symbol.ll
U test/MC/COFF/tricky-names.ll
G .
--- Recording mergeinfo for reverse merge of r195823 into '.':
G .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196036 91177308-0d34-0410-b5e6-96231b3b80d8
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r195941 | haoliu | 2013-11-28 18:11:22 -0800 (Thu, 28 Nov 2013) | 4 lines
AArch64: The pattern match should check the range of the immediate value.
Or we can generate some illegal instructions.
E.g. shrn2 v0.4s, v1.2d, #35. The legal range should be in [1, 16].
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r195939 | jiangning | 2013-11-28 17:38:08 -0800 (Thu, 28 Nov 2013) | 2 lines
Add missing test case for bsl_f64 support of AArch64 NEON.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196031 91177308-0d34-0410-b5e6-96231b3b80d8
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r195938 | jiangning | 2013-11-28 17:37:15 -0800 (Thu, 28 Nov 2013) | 3 lines
Add missing pattern for supporting intrinsic function vbsl_f64 with
argument double floating point.
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r195936 | kevinqin | 2013-11-28 17:29:16 -0800 (Thu, 28 Nov 2013) | 1 line
[AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196028 91177308-0d34-0410-b5e6-96231b3b80d8
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r195932 | d0k | 2013-11-28 11:58:56 -0800 (Thu, 28 Nov 2013) | 3 lines
Silence sign-compare warning and reduce nesting.
No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196027 91177308-0d34-0410-b5e6-96231b3b80d8
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r195905 | jiangning | 2013-11-27 17:34:55 -0800 (Wed, 27 Nov 2013) | 3 lines
Remove the variable only used by assert to avoid the build failure
caused by build options [-Werror,-Wunused-variable].
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196026 91177308-0d34-0410-b5e6-96231b3b80d8
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r195903 | haoliu | 2013-11-27 17:07:45 -0800 (Wed, 27 Nov 2013) | 2 lines
AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
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r196004 | void | 2013-11-30 19:36:07 -0800 (Sat, 30 Nov 2013) | 3 lines
Use 'unsigned char' to get this past gcc error message:
error: invalid conversion from 'unsigned char' to '{anonymous}::Sequence'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196005 91177308-0d34-0410-b5e6-96231b3b80d8
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r195590 | chapuni | 2013-11-24 16:52:46 -0800 (Sun, 24 Nov 2013) | 1 line
SparcFrameLowering.cpp: Prune 'DL' [-Wunused-variable]
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r195915 | dsanders | 2013-11-28 01:36:44 -0800 (Thu, 28 Nov 2013) | 2 lines
As myself as code-owner of the MIPS backend (lib/Target/Mips/*)
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r195677 | dpeixott | 2013-11-25 11:11:13 -0800 (Mon, 25 Nov 2013) | 41 lines
ARM integrated assembler generates incorrect nop opcode
This patch fixes a bug in the assembler that was causing bad code to
be emitted. When switching modes in an assembly file (e.g. arm to
thumb mode) we would always emit the opcode from the original mode.
Consider this small example:
$ cat align.s
.code 16
foo:
add r0, r0
.align 3
add r0, r0
$ llvm-mc -triple armv7-none-linux align.s -filetype=obj -o t.o
$ llvm-objdump -triple thumbv7 -d t.o
Disassembly of section .text:
foo:
0: 00 44 add r0, r0
2: 00 f0 20 e3 blx #4195904
6: 00 00 movs r0, r0
8: 00 44 add r0, r0
This shows that we have actually emitted an arm nop (e320f000)
instead of a thumb nop. Unfortunately, this encodes to a thumb
branch which causes bad things to happen when compiling assembly
code with align directives.
The fix is to notify the ARMAsmBackend when we switch mode. The
MCMachOStreamer was already doing this correctly. This patch makes
the same change for the MCElfStreamer.
There is still a bug in the way nops are emitted for alignment
because the MCAlignment fragment does not store the correct mode.
The ARMAsmBackend will emit nops for the last mode it knew about. In
the example above, we still generate an arm nop if we add a `.code
32` to the end of the file.
PR18019
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196001 91177308-0d34-0410-b5e6-96231b3b80d8
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r195881 | tstellar | 2013-11-27 13:23:39 -0800 (Wed, 27 Nov 2013) | 3 lines
R600: Expand vector FABS
NOTE: This is a candidate for the 3.4 branch.
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r195879 | tstellar | 2013-11-27 13:23:29 -0800 (Wed, 27 Nov 2013) | 6 lines
R600/SI: Use SGPR_32 register class for 32-bit SMRD outputs
Writing to the M0 register from an SMRD instruction hangs the GPU, so
we need to use the SGPR_32 register class, which does not include M0.
NOTE: This is a candidate for the 3.4 branch.
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r195878 | tstellar | 2013-11-27 13:23:20 -0800 (Wed, 27 Nov 2013) | 3 lines
R600: Add support for ISD::FROUND
NOTE: This is a candidate for the 3.4 branch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195998 91177308-0d34-0410-b5e6-96231b3b80d8
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r195843 | jiangning | 2013-11-27 06:02:25 -0800 (Wed, 27 Nov 2013) | 2 lines
Fix the AArch64 NEON bug exposed by checking constant integer argument range of ACLE intrinsics.
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r195812 | silvas | 2013-11-26 20:55:23 -0800 (Tue, 26 Nov 2013) | 3 lines
[docs] Mention gotcha regarding implicit BB numbering
Impetus for the clarification by Mikael Lyngvig.
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r195803 | mcrosier | 2013-11-26 17:45:58 -0800 (Tue, 26 Nov 2013) | 1 line
[AArch64] Add support for NEON scalar floating-point absolute difference.
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r195788 | mcrosier | 2013-11-26 14:17:37 -0800 (Tue, 26 Nov 2013) | 2 lines
[AArch64] Add support for NEON scalar floating-point to integer convert
instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195993 91177308-0d34-0410-b5e6-96231b3b80d8
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r195787 | arnolds | 2013-11-26 14:11:23 -0800 (Tue, 26 Nov 2013) | 8 lines
LoopVectorizer: Truncate i64 trip counts of i32 phis if necessary
In signed arithmetic we could end up with an i64 trip count for an i32 phi.
Because it is signed arithmetic we know that this is only defined if the i32
does not wrap. It is therefore safe to truncate the i64 trip count to a i32
value.
Fixes PR18049.
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r195834 | whitequark | 2013-11-27 03:03:18 -0800 (Wed, 27 Nov 2013) | 11 lines
[OCaml] Embed rpath into stub libraries and native executables
This commit embeds a set of linker flags with hardcoded paths to
the LLVM shared library on --enable-shared builds into .cmxa files
and stub dynamic libraries. This solution closely follows existing
rules for rpath in the LLVM tools, which had to be modified because
of differences in toolchain.
Without this patch, OCaml tests as well as opam bindings broke,
as neither of those updates LD_LIBRARY_PATH to include
the $prefix/lib directory.
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r195782 | whitequark | 2013-11-26 12:40:34 -0800 (Tue, 26 Nov 2013) | 1 line
[OCaml] Embed the flags necessary for linking with libLLVM.so into .cmxa files
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r195576 | venkatra | 2013-11-24 12:23:25 -0800 (Sun, 24 Nov 2013) | 2 lines
[Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of sethi+or. This generates correct code for both sparc32 and sparc64.
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r195575 | venkatra | 2013-11-24 12:07:35 -0800 (Sun, 24 Nov 2013) | 2 lines
[Sparc]: Implement LEA pattern for sparcv9.
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r195574 | venkatra | 2013-11-24 10:41:49 -0800 (Sun, 24 Nov 2013) | 2 lines
[SparcV9]: Do not emit .register directives for global registers that are clobbered by calls but not used in the function itself.
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r195573 | venkatra | 2013-11-24 09:41:41 -0800 (Sun, 24 Nov 2013) | 2 lines
[SparcV9] Enable custom lowering of DYNAMIC_STACKALLOC in sparc64.
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r195798 | rafael | 2013-11-26 17:18:37 -0800 (Tue, 26 Nov 2013) | 9 lines
Use simple section names for COMDAT sections on COFF.
With this patch we use simple names for COMDAT sections (like .text or .bss).
This matches the MSVC behavior.
When merging it is the COMDAT symbol that is used to decide if two sections
should be merged, so there is no point in building a fancy name.
This survived a bootstrap on mingw32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195823 91177308-0d34-0410-b5e6-96231b3b80d8
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r195148 | rafael | 2013-11-19 11:52:52 -0800 (Tue, 19 Nov 2013) | 15 lines
Support multiple COFF sections with the same name but different COMDAT.
This is the first step to fix pr17918.
It extends the .section directive a bit, inspired by what the ELF one looks
like. The problem with using linkonce is that given
.section foo
.linkonce....
.section foo
.linkonce
we would already have switched sections when getting to .linkonce. The cleanest
solution seems to be to add the comdat information in the .section itself.
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r195779 | hliao | 2013-11-26 12:31:31 -0800 (Tue, 26 Nov 2013) | 7 lines
Fix PR18054
- Fix bug in (vsext (vzext x)) -> (vsext x) in SIGN_EXTEND_IN_REG
lowering where we need to check whether x is a vector type (in-reg
type) of i8, i16 or i32; otherwise, that optimization is not valid.
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r195791 | nadav | 2013-11-26 14:24:25 -0800 (Tue, 26 Nov 2013) | 4 lines
PR1860 - We can't save a list of ExtractElement instructions to CSE because some of these instructions
may be removed and optimized in future iterations. Instead we save a list of basic blocks that we need to CSE.
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r195773 | nadav | 2013-11-26 09:29:19 -0800 (Tue, 26 Nov 2013) | 6 lines
PR18060 - When we RAUW values with ExtractElement instructions in some cases
we generate PHI nodes with multiple entries from the same basic block but
with different values. Enabling CSE on ExtractElement instructions make sure
that all of the RAUWed instructions are the same.
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r195769 | dyatkovskiy | 2013-11-26 08:11:03 -0800 (Tue, 26 Nov 2013) | 27 lines
PR17925 bugfix.
Short description.
This issue is about case of treating pointers as integers.
We treat pointers as different if they references different address space.
At the same time, we treat pointers equal to integers (with machine address
width). It was a point of false-positive. Consider next case on 32bit machine:
void foo0(i32 addrespace(1)* %p)
void foo1(i32 addrespace(2)* %p)
void foo2(i32 %p)
foo0 != foo1, while
foo1 == foo2 and foo0 == foo2.
As you can see it breaks transitivity. That means that result depends on order
of how functions are presented in module. Next order causes merging of foo0
and foo1: foo2, foo0, foo1
First foo0 will be merged with foo2, foo0 will be erased. Second foo1 will be
merged with foo2.
Depending on order, things could be merged we don't expect to.
The fix:
Forbid to treat any pointer as integer, except for those, who belong to address space 0.
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r195424 | haoliu | 2013-11-22 00:47:22 -0800 (Fri, 22 Nov 2013) | 4 lines
Fix the bugs about AArch64 Load/Store vector types and bitcast between i64 and vector types.
e.g. "%tmp = load <2 x i64>* %ptr" can't be selected.
"%tmp = bitcast i64 %in to <2 x i32>" can't be selected.
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r195408 | jiangning | 2013-11-21 18:45:13 -0800 (Thu, 21 Nov 2013) | 2 lines
For AArch64 back-end instruction selection, lower Neon_Lowxxx with EXTRCT_SUBREG.
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r195713 | kevinqin | 2013-11-25 18:33:42 -0800 (Mon, 25 Nov 2013) | 1 line
[AArch64]Implement 128 bit register copy with NEON.
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r195684 | rafael | 2013-11-25 12:50:03 -0800 (Mon, 25 Nov 2013) | 3 lines
Do the string comparison in the constructor instead of once per nop.
Thanks to Roman Divacky for the suggestion.
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r195682 | rafael | 2013-11-25 12:46:18 -0800 (Mon, 25 Nov 2013) | 1 line
Use -triple to fix the test on non-ELF hosts.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195745 91177308-0d34-0410-b5e6-96231b3b80d8
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r195469 | dsanders | 2013-11-22 07:47:18 -0800 (Fri, 22 Nov 2013) | 4 lines
[mips][msa] Add test case that should have been added in r195456.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195744 91177308-0d34-0410-b5e6-96231b3b80d8
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r195456 | dsanders | 2013-11-22 05:22:52 -0800 (Fri, 22 Nov 2013) | 4 lines
Fix typo in a comment added in r195455.
Credit to Matheus Almeida for spotting it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195743 91177308-0d34-0410-b5e6-96231b3b80d8
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r195444 | dsanders | 2013-11-22 03:24:50 -0800 (Fri, 22 Nov 2013) | 4 lines
[mips][msa] Float vector constants cannot use ldi.[wd] directly. Bitcast from the appropriate integer vector type.
Fixes an instruction selection failure detected by llvm-stress.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195742 91177308-0d34-0410-b5e6-96231b3b80d8
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r195364 | dsanders | 2013-11-21 08:11:31 -0800 (Thu, 21 Nov 2013) | 12 lines
[mips][msa] Fix a corner case in performORCombine() when combining nodes into VSELECT.
Mask == ~InvMask asserts if the width of Mask and InvMask differ.
The combine isn't valid (with two exceptions, see below) if the widths differ
so test for this before testing Mask == ~InvMask.
In the specific cases of Mask=~0 and InvMask=0, as well as Mask=0 and
InvMask=~0, the combine is still valid. However, there are more appropriate
combines that could be used in these cases such as folding x & 0 to 0, or
x & ~0 to x.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195741 91177308-0d34-0410-b5e6-96231b3b80d8
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