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* Work on LiveRange instead of LiveInterval where possibleMatthias Braun2013-10-106-69/+63
* Change MachineVerifier to work on LiveRange + LiveIntervalMatthias Braun2013-10-101-92/+117
* Pass LiveQueryResult by valueMatthias Braun2013-10-1010-117/+125
* Refactor LiveInterval: introduce new LiveRange classMatthias Braun2013-10-104-217/+235
* Rename LiveRange to LiveInterval::SegmentMatthias Braun2013-10-1016-369/+366
* Rename parameter: defined regs are not incoming.Matthias Braun2013-10-102-18/+17
* test commitSriram Murali2013-10-101-2/+4
* Use getPointerSizeInBits() rather than 8 * getPointerSize()Matt Arsenault2013-10-101-2/+3
* Fix grammar / missing wordsMatt Arsenault2013-10-101-2/+3
* Debug Info: In DIBuilder, the context field of subprogram is updated to useManman Ren2013-10-108-12/+56
* Add comments to debug info testing case.Manman Ren2013-10-101-0/+8
* R600: Fix trunc i64 to i32 on SIMatt Arsenault2013-10-102-0/+17
* Provide msbuild integration for vs2013.Hans Wennborg2013-10-104-1/+49
* Fix msbuild integration install script.Hans Wennborg2013-10-101-2/+5
* R600/SI: Implement SIInstrInfo::verifyInstruction() for VOP*Tom Stellard2013-10-105-4/+142
* R600/SI: Use -verify-machineinstrs for most testsTom Stellard2013-10-1084-86/+86
* R600/SI: Define a separate MIMG instruction for each possible output value typeTom Stellard2013-10-105-35/+90
* R600/SI: Mark the EXEC register as reservedTom Stellard2013-10-101-0/+1
* R600: Use StructurizeCFGPass for non SI targetsTom Stellard2013-10-106-2/+18
* Implement AArch64 vector load/store multiple N-element structure class SIMD(l...Hao Liu2013-10-1015-3/+2827
* Revert "Implement AArch64 vector load/store multiple N-element structure clas...Rafael Espindola2013-10-1015-2808/+3
* Implement AArch64 vector load/store multiple N-element structure class SIMD(l...Hao Liu2013-10-1015-3/+2808
* ARM: Put isV8EligibleForIT into the llvm namespace. While there make it inline.Benjamin Kramer2013-10-101-2/+4
* Disable function padding to get this test to pass on atom.Benjamin Kramer2013-10-101-1/+1
* ARM: correct liveness flags during ARMLoadStoreOptTim Northover2013-10-102-0/+117
* Allow non-AVX form of pmovmskb to take a GR64 operand.Craig Topper2013-10-102-0/+6
* Remove duplicate instructions.Craig Topper2013-10-101-16/+0
* Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables.Craig Topper2013-10-101-1/+1
* [mips] Do not generate INS/EXT nodes if target does not have support forAkira Hatanaka2013-10-093-17/+25
* Revert "llvm-c: Make target initializer functions external functions in lib."Rui Ueyama2013-10-093-55/+36
* Debug Info: In DIBuilder, the context and type fields of template_type andManman Ren2013-10-095-54/+76
* llvm-c: Make target initializer functions external functions in lib.Anders Waldenborg2013-10-093-36/+55
* Debug Info: In DIBuilder, the context field of a forward decl is updatedManman Ren2013-10-092-35/+47
* Add missing releases.Bill Wendling2013-10-091-0/+2
* Flip the ownership of MCStreamer and MCTargetStreamer.Benjamin Kramer2013-10-092-4/+4
* Fix a bug in Dead Argument Elimination.Shuxin Yang2013-10-092-0/+34
* Add a GlobalAlias::isValidLinkage to reduce code duplication.Rafael Espindola2013-10-093-6/+7
* [Sparc] Disable tail call optimization for sparc64.Venkatraman Govindaraju2013-10-092-0/+43
* Test commit. Remove whitespace from otherwise empty lines.Greg Bedwell2013-10-091-2/+2
* AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.Elena Demikhovsky2013-10-095-65/+192
* AArch64: enable MISched by default.Tim Northover2013-10-0912-93/+101
* AArch64: migrate ADRP relaxation test to be llvm-mc only.Tim Northover2013-10-092-27/+18
* More x86 disassembler filtering cleanup.Craig Topper2013-10-091-4/+1
* Add missing HasAVX512 predicate.Andrew Trick2013-10-091-2/+2
* Remove some old filters from the x86 disassembler table builder.Craig Topper2013-10-091-6/+0
* Replace a couple instructions with patterns referring to other instructions w...Craig Topper2013-10-091-16/+11
* Use AVX512PIi8 for the alt forms of vcmp instructions. This adds the TB prefi...Craig Topper2013-10-091-4/+4
* Mark some instructions as CodeGenOnly since they aren't needed by the assembl...Craig Topper2013-10-091-65/+73
* Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. Thi...Craig Topper2013-10-095-11/+19
* Add a paragraph about MCTargetStreamer.Rafael Espindola2013-10-091-0/+7
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