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* Add MCObjectFileInfo and sink the MCSections initialization code fromEvan Cheng2011-07-2027-840/+900
| | | | | | | | | TargetLoweringObjectFileImpl down to MCObjectFileInfo. TargetAsmInfo is done to one last method. It's *almost* gone! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135569 91177308-0d34-0410-b5e6-96231b3b80d8
* indvars: Added getInsertPointForUses to find a valid place to truncate the IV.Andrew Trick2011-07-202-15/+71
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135568 91177308-0d34-0410-b5e6-96231b3b80d8
* indvars -disable-iv-rewrite: Add NarrowIVDefUse to cache def-useAndrew Trick2011-07-201-54/+61
| | | | | | | | info. Holding Use* pointers is bad form even though it happened to work in this case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135566 91177308-0d34-0410-b5e6-96231b3b80d8
* X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, ↵NAKAMURA Takumi2011-07-201-1/+2
| | | | | | to appease test/CodeGen/X86 on cygwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135564 91177308-0d34-0410-b5e6-96231b3b80d8
* New pointer rotate test.Eric Christopher2011-07-201-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135562 91177308-0d34-0410-b5e6-96231b3b80d8
* Extra semi-colon.Eric Christopher2011-07-201-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135561 91177308-0d34-0410-b5e6-96231b3b80d8
* indvars test case for r135558.Andrew Trick2011-07-201-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135559 91177308-0d34-0410-b5e6-96231b3b80d8
* indvars -disable-iv-rewrite fix: derived GEP IVsAndrew Trick2011-07-202-6/+35
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135558 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't leak CodeGenInfos.Benjamin Kramer2011-07-201-1/+3
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* Change name of class.Akira Hatanaka2011-07-201-23/+23
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* Define classes for definitions of atomic instructions.Akira Hatanaka2011-07-201-106/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135546 91177308-0d34-0410-b5e6-96231b3b80d8
* Build and install the archive when building the Apple way.Bill Wendling2011-07-191-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135538 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower memory barriers to sync instructions.Akira Hatanaka2011-07-194-2/+47
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135537 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an obvious typo that's preventing x86 (32-bit) from using .literal16.Evan Cheng2011-07-192-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135535 91177308-0d34-0410-b5e6-96231b3b80d8
* PR10386: Don't try to split an edge from an indirectbr.Eli Friedman2011-07-192-2/+61
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135534 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix off-by-one.Benjamin Kramer2011-07-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135533 91177308-0d34-0410-b5e6-96231b3b80d8
* Tweak ARM assembly parsing and printing of MSR instruction.Jim Grosbach2011-07-197-50/+86
| | | | | | | | | The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
* Distinguish between two copies of one inlined variable.Devang Patel2011-07-194-3/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135528 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing of MRS instruction.Jim Grosbach2011-07-194-10/+24
| | | | | | | | | Teach the parser to recognize the APSR and SPSR system register names. Add and update tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135527 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance the FixedLengthDecoder to be able to generate plausible-looking ↵Owen Anderson2011-07-194-112/+140
| | | | | | decoders for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135524 91177308-0d34-0410-b5e6-96231b3b80d8
* Change variable name.Akira Hatanaka2011-07-191-3/+3
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* ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.Jim Grosbach2011-07-193-9/+22
| | | | | | | Add range checking to the immediate operands. Update tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135521 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL orAkira Hatanaka2011-07-192-29/+30
| | | | | | | ANDi, when the instruction does not have any immediate operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135520 91177308-0d34-0410-b5e6-96231b3b80d8
* Move mr[r]c[2] ARM tests and tidy up a bit.Jim Grosbach2011-07-192-10/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135517 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM testcases for MOVT.Jim Grosbach2011-07-192-0/+15
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* Use descriptive variable names. Akira Hatanaka2011-07-191-154/+177
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* ARM assembly parsing for MOV (register).Jim Grosbach2011-07-193-19/+46
| | | | | | | | | Correct the handling of the 's' suffix when parsing ARM mode. It's only a truly separate opcode in Thumb. Add test cases to make sure we handle the s and condition suffices correctly, including diagnostics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135513 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up.Jim Grosbach2011-07-191-12/+8
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* Tighten conditional for 'mov' cc_out.Jim Grosbach2011-07-191-1/+2
| | | | | | | | Make sure we only clobber the cc_out operand if it is indeed a default non-setting operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135506 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r135457. This needs llvm-gcc change, that I forgot to check-in ↵Devang Patel2011-07-194-5/+32
| | | | | | yesterday. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135504 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing for MOV (immediate).Jim Grosbach2011-07-197-21/+99
| | | | | | | | | Add range checking for the immediate operand and handle the "mov" mnemonic choosing between encodings based on the value of the immediate. Add tests for fixups, encoding choice and values, and diagnostic for out of range values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace.Jim Grosbach2011-07-191-1/+1
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* Remove unused code.Jim Grosbach2011-07-191-54/+3
| | | | | | | cc_out and pred operands are added during parsing via custom C++ now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135497 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comments.Akira Hatanaka2011-07-191-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135496 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove redundant instructions.Akira Hatanaka2011-07-192-26/+17
| | | | | | | | | | - In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the instruction being expanded, instead of masking it in thisMBB. - Remove redundant Or in EmitAtomicCmpSwap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135495 91177308-0d34-0410-b5e6-96231b3b80d8
* Separate code that modifies control flow from code that adds instruction to Akira Hatanaka2011-07-191-18/+18
| | | | | | | | basic blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135490 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM range checking for so_imm operands in assembly parsing.Jim Grosbach2011-07-192-0/+15
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* Revert "Make a provision to encode inline location in a variable. This will ↵Bob Wilson2011-07-194-32/+5
| | | | | | | | enable dwarf writer to easily distinguish between two instances of a inlined variable in one basic block." This reverts commit 9fec5e346efdf744b151ae6604f912908315fa7a. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135486 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Update docs to reflect r135457."Bob Wilson2011-07-191-3/+1
| | | | | | This reverts commit ba034c0a2e71303c7cf3f43ca8e69dc8436b32e2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135485 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert ConstantFoldGetElementPtr to use ArrayRef.Jay Foad2011-07-193-27/+25
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* Convert SimplifyGEPInst to use ArrayRef.Jay Foad2011-07-195-11/+15
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* Convert gep_type_begin and gep_type_end to use ArrayRef.Jay Foad2011-07-193-9/+11
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* Convert TargetData::getIndexedOffset to use ArrayRef.Jay Foad2011-07-1911-30/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135478 91177308-0d34-0410-b5e6-96231b3b80d8
* Use ArrayRef in ConstantFoldInstOperands and ConstantFoldCall.Jay Foad2011-07-199-43/+43
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135477 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsics for the zext / sext instructions.Richard Osborne2011-07-193-7/+47
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135476 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsics for the testct, testwct instructions.Richard Osborne2011-07-193-1/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135475 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsics for the peek and endin instructions.Richard Osborne2011-07-193-1/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135474 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove bogus test: for all possible inputs of %X, the 'sub nsw' is guaranteedNick Lewycky2011-07-191-11/+0
| | | | | | | to perform a signed wrap. Don't rely on any particular handling of that case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135471 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-1974-314/+641
| | | | | | | | (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
* Make EmitAtomic functions return the correct MachineBasicBlocks so thatAkira Hatanaka2011-07-191-22/+28
| | | | | | | | | ExpandISelPseudos::runOnMachineFunction does not visit instructions that have just been added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135465 91177308-0d34-0410-b5e6-96231b3b80d8
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