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* Switch MCAssembler to method names starting w/ lower-case.Jim Grosbach2011-12-065-49/+49
| | | | | | per http://llvm.org/docs/CodingStandards.html#ll_naming git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145873 91177308-0d34-0410-b5e6-96231b3b80d8
* Simple branch relaxation for Thumb2 Bcc instructions.Jim Grosbach2011-12-051-3/+24
| | | | | | | Not right yet, as the rules for when to relax in the MCAssembler aren't (yet) correct for ARM. This is a step in the proper direction, though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145871 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up.Jim Grosbach2011-12-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145870 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence tsan false-positives (tsan can't track things which are only safe due toNick Lewycky2011-12-052-0/+5
| | | | | | | | memory fences) in statistics registration, which works the same way that ManagedStatic registration does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145869 91177308-0d34-0410-b5e6-96231b3b80d8
* Update comment.Chad Rosier2011-12-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145866 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerioChad Rosier2011-12-052-2/+18
| | | | | | | | where this would be bad as the backend shouldn't have a problem inlining small memcpys. rdar://10510150 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145865 91177308-0d34-0410-b5e6-96231b3b80d8
* Tweak ADDrr fix. Bad check for explicit .wJim Grosbach2011-12-052-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145863 91177308-0d34-0410-b5e6-96231b3b80d8
* Update tests for r145860. Add a few new ones.Jim Grosbach2011-12-052-1/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145861 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 prefer ADD register encoding T2 to T3 when possible.Jim Grosbach2011-12-051-0/+20
| | | | | | | rdar://10529664 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145860 91177308-0d34-0410-b5e6-96231b3b80d8
* Move 'returns_twice' definition into alphabetical place.Bill Wendling2011-12-051-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145854 91177308-0d34-0410-b5e6-96231b3b80d8
* Add definitions of 64-bit extract and insert instrucions and makeAkira Hatanaka2011-12-053-12/+72
| | | | | | | | | PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145853 91177308-0d34-0410-b5e6-96231b3b80d8
* Split ExtIns into two base classes and have instructions EXT and INS derive fromAkira Hatanaka2011-12-051-17/+21
| | | | | | | | them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145852 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.Jim Grosbach2011-12-052-0/+22
| | | | | | | rdar://10529348 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145851 91177308-0d34-0410-b5e6-96231b3b80d8
* Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 andAkira Hatanaka2011-12-052-25/+29
| | | | | | | O32 with relocation-model=pic too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145850 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing for the rest of the VMUL data type aliases.Jim Grosbach2011-12-053-10/+139
| | | | | | | Finish up rdar://10522016. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145846 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix previous commit. Oops.Jim Grosbach2011-12-051-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145844 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. No functional change.Jim Grosbach2011-12-051-9/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145843 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assmebler parsing for two-operand VMUL instructions.Jim Grosbach2011-12-052-0/+11
| | | | | | | | | Combined destination and first source operand for f32 variant of the VMUL (by scalar) instruction. rdar://10522016 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145842 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the Dominators recalculate() function to only rely on GraphTraitsAnna Zaks2011-12-055-8/+20
| | | | | | | | | | | This is a patch by Guoping Long! As part of utilizing LLVM Dominator computation in Clang, made two changes to LLVM dominators tree implementation: - (1) Change the recalculate() template function to only rely on GraphTraits. - (2) Add a size() method to GraphTraits template class to query the number of nodes in the graph. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145837 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test case - this input used to crash because of duplicate generation of ↵Hal Finkel2011-12-051-0/+191
| | | | | | SPILL_CRs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145820 91177308-0d34-0410-b5e6-96231b3b80d8
* enable PPC register scavenging by default (update tests and remove some FIXMEs)Hal Finkel2011-12-059-37/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145819 91177308-0d34-0410-b5e6-96231b3b80d8
* don't include CR bit subregs in callee-saved listHal Finkel2011-12-051-16/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145818 91177308-0d34-0410-b5e6-96231b3b80d8
* remove wasted space for extra bit copies of CR2 subregsHal Finkel2011-12-051-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145817 91177308-0d34-0410-b5e6-96231b3b80d8
* add register pressure for CR regsHal Finkel2011-12-051-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145816 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a little heuristic to Value::isUsedInBasicBlock to speed it up for small ↵Benjamin Kramer2011-12-052-8/+14
| | | | | | | | | | basic blocks. - Calling getUser in a loop is much more expensive than iterating over a few instructions. - Use it instead of the open-coded loop in AddrModeMatcher. - 5% speedup on ARMDisassembler.cpp Release builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145810 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86/pointer-vector.ll: Add explicit -mtriple=i686-linux.NAKAMURA Takumi2011-12-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145805 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR ↵Craig Topper2011-12-051-2/+2
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145804 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up and optimizations to the X86 shuffle lowering code. No functional ↵Craig Topper2011-12-051-52/+36
| | | | | | change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145803 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for vectors of pointers.Nadav Rotem2011-12-0526-71/+631
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145801 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix table of contents.Jakub Staszak2011-12-041-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145793 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 'llvm.expect' intrinsic description.Jakub Staszak2011-12-041-0/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145792 91177308-0d34-0410-b5e6-96231b3b80d8
* Add inline subprogram names to the name lookup table since they mayEric Christopher2011-12-041-0/+4
| | | | | | not get there any other way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145789 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix 80-column issues.Bob Wilson2011-12-041-4/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145783 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit the ctors in the proper order on ARM/EABI.Anton Korobeynikov2011-12-038-18/+52
| | | | | | | | | Maybe some targets should use this as well. Patch by Evgeniy Stepanov! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145781 91177308-0d34-0410-b5e6-96231b3b80d8
* Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() sinceVenkatraman Govindaraju2011-12-032-1/+26
| | | | | | | AnalyzeBranch doesn't change the successor, just the order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145779 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify code. No functionality change.Benjamin Kramer2011-12-031-2/+1
| | | | | | -3% on ARMDissasembler.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145773 91177308-0d34-0410-b5e6-96231b3b80d8
* Clear the new cache.Benjamin Kramer2011-12-031-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145771 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a "seen blocks" cache to LVI to avoid a linear scan over the whole cache ↵Benjamin Kramer2011-12-031-1/+13
| | | | | | | | | just to remove no blocks from the maps. -15% on ARMDisassembler.cpp (Release build). It's not that great to add another layer of caching to the caching-heavy LVI but I don't see a better way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145770 91177308-0d34-0410-b5e6-96231b3b80d8
* Check for stack space more intelligently.Sanjoy Das2011-12-032-13/+43
| | | | | | | | | | libgcc sets the stack limit field in TCB to 256 bytes above the actual allocated stack limit. This means if the function's stack frame needs less than 256 bytes, we can just compare the stack pointer with the stack limit. This should result in lesser calls to __morestack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145766 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in the x86-32 code generated for segmented stacks.Sanjoy Das2011-12-032-14/+2
| | | | | | | | | | | Currently LLVM pads the call to __morestack with a add and sub of 8 bytes to esp. This isn't correct since __morestack expects the call to be followed directly by a ret. This commit also adjusts the relevant test-case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145765 91177308-0d34-0410-b5e6-96231b3b80d8
* Creating multiple JITs on X86 in multiple threads causes multiple writes (ofNick Lewycky2011-12-031-0/+2
| | | | | | | | | the same value) to this variable. This code could be refactored, but it doesn't matter since the old JIT is going away. Add tsan annotations to ignore the race. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145745 91177308-0d34-0410-b5e6-96231b3b80d8
* [arm-fast-isel] Unaligned stores of floats require special care.Chad Rosier2011-12-032-3/+40
| | | | | | rdar://10510150 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145742 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed deadstoreelimination bug where negative indices were incorrectly ↵Pete Cooper2011-12-032-1/+18
| | | | | | | | | | causing the optimisation to occur Turns out long long + unsigned long long is unsigned. Doh! Fixes http://llvm.org/bugs/show_bug.cgi?id=11455 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145731 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for constant folding the pow intrinsic.Chad Rosier2011-12-032-3/+15
| | | | | | rdar://10514247 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145730 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON VEXT aliases for data type suffices.Jim Grosbach2011-12-024-11/+58
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145726 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VEXT tighten up operand classes a bit.Jim Grosbach2011-12-021-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145722 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VST1 single lane assembly parsing.Jim Grosbach2011-12-022-4/+179
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145718 91177308-0d34-0410-b5e6-96231b3b80d8
* Test cases for 64-bit multiplication and division.Akira Hatanaka2011-12-021-0/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145717 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test cases to use FileCheck.Akira Hatanaka2011-12-029-81/+79
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145716 91177308-0d34-0410-b5e6-96231b3b80d8
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-0262-602/+728
| | | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
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