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* The ppc bots say this is the last broken line, so lets try one more :-(Rafael Espindola2013-04-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178849 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a SchedMachineModel for the PPC A2Hal Finkel2013-04-052-2/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178848 91177308-0d34-0410-b5e6-96231b3b80d8
* One more try before I just delete the macho bits until tomorrow.Rafael Espindola2013-04-052-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178847 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug in PEI's virtual-register scavengingHal Finkel2013-04-053-24/+84
| | | | | | | | | | | | | | | | | | | | This change fixes a bug that I introduced in r178058. After a register is scavenged using one of the available spills slots the instruction defining the virtual register needs to be moved to after the spill code. The scavenger has already processed the defining instruction so that registers killed by that instruction are available for definition in that same instruction. Unfortunately, after this, the scavenger needs to iterate through the spill code and then visit, again, the instruction that defines the now-scavenged register. In order to avoid confusion, the register scavenger needs the ability to 'back up' through the spill code so that it can again process the instructions in the appropriate order. Prior to this fix, once the scavenger reached the just-moved instruction, it would assert if it killed any registers because, having already processed the instruction, it believed they were undefined. Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar for diagnosing the problem and testing this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178845 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM scheduler model: Add scheduler info to more instructions and resourceArnold Schwaighofer2013-04-054-32/+67
| | | | | | descriptions for compares git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178844 91177308-0d34-0410-b5e6-96231b3b80d8
* More test loosening.Rafael Espindola2013-04-052-4/+4
| | | | | | Sorry for so many commits, but llvm is still building on my ppc vm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178843 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM scheduler model: Swift has varying latencies, uops for simple ALU opsArnold Schwaighofer2013-04-054-5/+57
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178842 91177308-0d34-0410-b5e6-96231b3b80d8
* Loosen this test too.Rafael Espindola2013-04-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178841 91177308-0d34-0410-b5e6-96231b3b80d8
* Loosen this test.Rafael Espindola2013-04-051-1/+1
| | | | | | | | | Looks like there is a big endian/little endian problem here. Loosen the test to try to get the bots green while llvm builds on a ppc qemu vm. The failure was in http://lab.llvm.org:8011/builders/clang-ppc64-elf-linux2/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178839 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove empty directory.Rafael Espindola2013-04-050-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178837 91177308-0d34-0410-b5e6-96231b3b80d8
* Move obj2yaml to tools to sort out make's dependencies.Rafael Espindola2013-04-059-4/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178835 91177308-0d34-0410-b5e6-96231b3b80d8
* Build obj2yaml with configure+make.Rafael Espindola2013-04-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178833 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test for obj2yaml in preparation for refactoring it.Rafael Espindola2013-04-051-0/+170
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178829 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up some confusing language, and use more realistic examples.Jakob Stoklund Olesen2013-04-051-5/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178828 91177308-0d34-0410-b5e6-96231b3b80d8
* RegisterPressure heuristics currently require signed comparisons.Andrew Trick2013-04-052-2/+230
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178823 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable DFSResult for ConvergingScheduler.Andrew Trick2013-04-051-2/+0
| | | | | | | | For now, just save the compile time since the ConvergingScheduler heuristics don't use this analysis. We'll probably enable it later after compile-time investigation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178822 91177308-0d34-0410-b5e6-96231b3b80d8
* MachineScheduler: format DEBUG output.Andrew Trick2013-04-051-22/+17
| | | | | | | I'm getting more serious about tuning and enabling on x86/ARM. Start by making the trace readable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178821 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorizer: Pass OperandValueKind information to the cost modelArnold Schwaighofer2013-04-042-2/+41
| | | | | | | | | | | | Pass down the fact that an operand is going to be a vector of constants. This should bring the performance of MultiSource/Benchmarks/PAQ8p/paq8p on x86 back. It had degraded to scalar performance due to my pervious shift cost change that made all shifts expensive on x86. radar://13576547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178809 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 cost model: Differentiate cost for vector shifts of constantsArnold Schwaighofer2013-04-044-0/+892
| | | | | | | | | | | | SSE2 has efficient support for shifts by a scalar. My previous change of making shifts expensive did not take this into account marking all shifts as expensive. This would prevent vectorization from happening where it is actually beneficial. With this change we differentiate between shifts of constants and other shifts. radar://13576547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178808 91177308-0d34-0410-b5e6-96231b3b80d8
* CostModel: Add parameter to instruction cost to further classify operand valuesArnold Schwaighofer2013-04-046-13/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On certain architectures we can support efficient vectorized version of instructions if the operand value is uniform (splat) or a constant scalar. An example of this is a vector shift on x86. We can efficiently support for (i = 0 ; i < ; i += 4) w[0:3] = v[0:3] << <2, 2, 2, 2> but not for (i = 0; i < ; i += 4) w[0:3] = v[0:3] << x[0:3] This patch adds a parameter to getArithmeticInstrCost to further qualify operand values as uniform or uniform constant. Targets can then choose to return a different cost for instructions with such operand values. A follow-up commit will test this feature on x86. radar://13576547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178807 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: revert 178722 for now.Manman Ren2013-04-043-15/+4
| | | | | | | | | | | | | | There is a difference for FORM_ref_addr between DWARF 2 and DWARF 3+. Since Eric is against guarding DWARF 2 ref_addr with DarwinGDBCompat, we are still in discussion on how to handle this. The correct solution is to update our header to say version 4 instead of version 2 and update tool chains as well. rdar://problem/13559431 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178806 91177308-0d34-0410-b5e6-96231b3b80d8
* typoAdrian Prantl2013-04-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178804 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the current PPC BCL definition to BCLalwaysHal Finkel2013-04-043-5/+5
| | | | | | | | | | | | BCL is normally a conditional branch-and-link instruction, but has an unconditional form (which is used in the SjLj code, for example). To make clear that this BCL instruction definition is specifically the special unconditional form (which does not meaningfully take a condition-register input), rename it to BCLalways. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178803 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Improve code generation for mixed-precision reciprocal sqrtHal Finkel2013-04-042-0/+75
| | | | | | | | The DAGCombine logic that recognized a/sqrt(b) and transformed it into a multiplication by the reciprocal sqrt did not handle cases where the sqrt and the division were separated by an fpext or fptrunc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178801 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Expand br_cc.Jyotsna Verma2013-04-041-0/+2
| | | | | | | | | | | | | | | It fixes following tests for Hexagon: CodeGen/Generic/2003-07-29-BadConstSbyte.ll CodeGen/Generic/2005-10-21-longlonggtu.ll CodeGen/Generic/2009-04-28-i128-cmp-crash.ll CodeGen/Generic/MachineBranchProb.ll CodeGen/Generic/builtin-expect.ll CodeGen/Generic/pr12507.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178794 91177308-0d34-0410-b5e6-96231b3b80d8
* Reassociate: Avoid iterator invalidation.Benjamin Kramer2013-04-041-7/+12
| | | | | | | | OpndPtrs stored pointers into the Opnd vector that became invalid when the vector grows. Store indices instead. Sadly I only have a large testcase that only triggers under valgrind, so I didn't include it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178793 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable 2010-10-01-crash.ll for Hexagon as the Hexagon frontend willJyotsna Verma2013-04-041-0/+1
| | | | | | | | never produce a byval parameter with size < 8 bytes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178792 91177308-0d34-0410-b5e6-96231b3b80d8
* Add back parsing of header charactestics.Rafael Espindola2013-04-043-1/+43
| | | | | | | | It had been dropped during the switch to yaml::IO. Also add a test going from yaml2obj to llvm-readobj. It can be extended as we add more fields/formats to yaml2obj. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178786 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add bru instruction.Richard Osborne2013-04-042-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178783 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] The RRegs register class is a superset of GRRegs.Richard Osborne2013-04-045-34/+94
| | | | | | | | | | At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
* Missing wordEli Bendersky2013-04-041-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178774 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid high-latency false CPSR dependencies even for tMOVSi.Jakob Stoklund Olesen2013-04-042-46/+134
| | | | | | | | | | | | | | | | | The Thumb2SizeReduction pass avoids false CPSR dependencies, except it still aggressively creates tMOVi8 instructions because they are so common. Avoid creating false CPSR dependencies even for tMOVi8 instructions when the the CPSR flags are known to have high latency. This allows integer computation to overlap floating point computations. Also process blocks in a reverse post-order and propagate high-latency flags to successors. <rdar://problem/13468102> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178773 91177308-0d34-0410-b5e6-96231b3b80d8
* FormattingEli Bendersky2013-04-041-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178771 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r178713Evan Cheng2013-04-046-29/+13
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* New-password-test commit.Stepan Dyatkovskiy2013-04-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178765 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use a mask for offsets when encoding instructionsVincent Lejeune2013-04-041-2/+5
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* R600: Fix wrong address when substituting ENDIFVincent Lejeune2013-04-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178762 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Take export into account when computing cf addressVincent Lejeune2013-04-042-0/+54
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178761 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate path to ASan/MSan symbolizer into test environment to produce ↵Alexey Samsonov2013-04-042-0/+10
| | | | | | useful reports on errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178749 91177308-0d34-0410-b5e6-96231b3b80d8
* Document the return value of SmallSet insert.Nadav Rotem2013-04-041-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178742 91177308-0d34-0410-b5e6-96231b3b80d8
* Add SPARC v9 support for select on 64-bit compares.Jakob Stoklund Olesen2013-04-045-5/+57
| | | | | | | | | | | This requires v9 cmov instructions using the %xcc flags instead of the %icc flags. Still missing: - Select floats on %xcc flags. - Select i64 on %fcc flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178737 91177308-0d34-0410-b5e6-96231b3b80d8
* Explicitly add -Wl,--export-all-symbols on mingw/cygwin.Rafael Espindola2013-04-041-0/+3
| | | | | | | Looks like cmake on windows is not expanding ENABLE_EXPORTS to -Wl,--export-all-symbols on mingw or cygwin, so add this back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178730 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't export symbols in every binary on linux.Rafael Espindola2013-04-044-3/+7
| | | | | | | | | | | | On freebsd this makes sure that symbols are exported on the binaries that need them. The net result is that we should get symbols in the binaries that need them on every platform. On linux x86-64 this reduces the size of the bin directory from 262MB to 250MB. Patch by Stephen Checkoway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178725 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: according to DWARF 2, FORM_ref_addr the same size as an address onManman Ren2013-04-043-4/+15
| | | | | | | | | | | | the target system. It was hard-coded to 4 bytes before. I can't get llvm to generate a ref_addr on a reasonably sized testing case. rdar://problem/13559431 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178722 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactored out the helper method FindPredecessorAutoreleaseWithSafePath from ↵Michael Gottesman2013-04-031-25/+45
| | | | | | | | ObjCARCOpt::OptimizeReturns. Now ObjCARCOpt::OptimizeReturns is easy to read and reason about. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178715 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactored out the helper function FindPredecessorRetainWithSafePath from ↵Michael Gottesman2013-04-031-18/+32
| | | | | | ObjCARCOpt::OptimizeReturns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178714 91177308-0d34-0410-b5e6-96231b3b80d8
* Make it possible to include llvm-c without including C++ headers. Patch by ↵Evan Cheng2013-04-036-13/+29
| | | | | | Filip Pizlo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178713 91177308-0d34-0410-b5e6-96231b3b80d8
* Small cleanups.Michael Gottesman2013-04-031-14/+14
| | | | | | | | Cleaned up trailing whitespace and added extra slashes in front of a function level comment so that it follow the convention of having 3 slashes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178712 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactored out a part of ObjCARCOpt::OptimizeReturns into its own method ↵Michael Gottesman2013-04-031-22/+33
| | | | | | HasSafePathToPredecessorCall. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178710 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed an old comment.Michael Gottesman2013-04-031-7/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178709 91177308-0d34-0410-b5e6-96231b3b80d8
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