aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Add support to BBVectorize for vectorizing selects.Hal Finkel2012-04-133-0/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154700 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for Hexagon Architectural feature, New Value Jump.Sirish Pande2012-04-137-10/+684
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154696 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass to replace tranfer/copy instructions into combine instruction where ↵Sirish Pande2012-04-135-0/+484
| | | | | | possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154695 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce malloc traffic in DwarfAccelTableBenjamin Kramer2012-04-132-58/+28
| | | | | | | | | - Don't copy offsets into HashData, the underlying vector won't change once the table is finalized. - Allocate HashData and HashDataContents in a BumpPtrAllocator. - Allocate string map entries in the same allocator. - Random cleanups. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154694 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for Hexagon backend.Tony Linthicum2012-04-131-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154692 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for Hexagon backend.Tony Linthicum2012-04-131-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154691 91177308-0d34-0410-b5e6-96231b3b80d8
* On Darwin targets, only use vfma etc. if the source use fma() intrinsic ↵Evan Cheng2012-04-132-3/+6
| | | | | | explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154689 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some comments, and fix a few places that missed setting Changed.Dan Gohman2012-04-131-2/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154687 91177308-0d34-0410-b5e6-96231b3b80d8
* For ARM disassembly only print 32 unsigned bits for the address of branchKevin Enderby2012-04-131-2/+2
| | | | | | | | targets so if the branch target has the high bit set it does not get printed as: beq 0xffffffff8008c404 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154685 91177308-0d34-0410-b5e6-96231b3b80d8
* Consider ObjC runtime calls objc_storeWeak and others which make a copy ofDan Gohman2012-04-132-14/+160
| | | | | | | | their argument as "escape" points for objc_retainBlock optimization. This fixes rdar://11229925. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154682 91177308-0d34-0410-b5e6-96231b3b80d8
* By default, use Early-CSE instead of GVN for vectorization cleanup.Hal Finkel2012-04-131-2/+9
| | | | | | | | | | As has been suggested by Duncan and others, Early-CSE and GVN should do similar redundancy elimination, but Early-CSE is much less expensive. Most of my autovectorization benchmarks show a performance regresion, but all of these are < 0.1%, and so I think that it is still worth using the less expensive pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154673 91177308-0d34-0410-b5e6-96231b3b80d8
* Catch the Python exception when subprocess.Popen is failing.Sylvestre Ledru2012-04-131-1/+6
| | | | | | | | | | For example, if llc cannot be found, the full python stacktrace is displayed and no interesting information are provided. + fail the process when an exception occurs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154665 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused variable.Benjamin Kramer2012-04-131-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154661 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence various build warnings from Hexagon backend that show up in release ↵Craig Topper2012-04-135-240/+220
| | | | | | builds. Mostly converting 'assert(0)' to 'llvm_unreachable' to silence warnings about missing returns. Also fold some variable declarations into asserts to prevent the variables from being unused in release builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154660 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix target specific intrinsic handling to adjust intrinsic number before ↵Craig Topper2012-04-131-9/+15
| | | | | | doing attribute table lookup. Also fix attribute table lookup to handle 'invalid' intrinsic correctly. Fixes PR12542 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154658 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove getElfArchType from ELF.h. It's only used in ELFObjectFile.cpp and ↵Craig Topper2012-04-131-9/+0
| | | | | | there's already a copy there. ELF.h was hiding the one there and causing an unused function warning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154657 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the new Use-aware dominates method to apply the objc runtimeDan Gohman2012-04-132-8/+23
| | | | | | | | library return value optimization for phi uses. Even when the phi itself is not dominated, the specific use may be dominated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154647 91177308-0d34-0410-b5e6-96231b3b80d8
* Code-gen may inject code into the IR before it emits the ASM. The linkerBill Wendling2012-04-131-0/+6
| | | | | | | | | obviously cannot know that this code is present, let alone used. So prevent the internalize pass from internalizing those global values which code-gen may insert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154645 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't move objc_autorelease calls past autorelease pool boundaries whenDan Gohman2012-04-132-7/+121
| | | | | | | | optimizing autorelease calls on phi nodes with null operands. This fixes rdar://11207070. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154642 91177308-0d34-0410-b5e6-96231b3b80d8
* Def here is an Instruction, so !isa<Instruction>(Def) is always false,Dan Gohman2012-04-131-3/+2
| | | | | | | as Eli noticed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154641 91177308-0d34-0410-b5e6-96231b3b80d8
* Add forms of dominates and isReachableFromEntry that accept a UseDan Gohman2012-04-122-0/+84
| | | | | | | | | directly instead of a user Instruction. This allows them to test whether a def dominates a particular operand if the user instruction is a PHI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154631 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a few more places in the ARM disassembler so that branches getKevin Enderby2012-04-122-4/+30
| | | | | | | symbolic operands added when using the C disassembler API. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154628 91177308-0d34-0410-b5e6-96231b3b80d8
* Update CMake build.Ted Kremenek2012-04-122-4/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154622 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: fix CMake error.Evandro Menezes2012-04-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154620 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable Hexagon test temporarily.Sirish Pande2012-04-1210-10/+20
| | | | | | | | | | | | | There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA). This assert needs to addressed for post RA scheduler. Until that assert is addressed, any passes that uses post ra scheduler will fail. So, I am temporarily disabling the hexagon tests until that fix is in. The assert is as follows: assert(!MI->isTerminator() && !MI->isLabel() && "Cannot schedule terminators or labels!"); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154617 91177308-0d34-0410-b5e6-96231b3b80d8
* HexagonPacketizer patch.Sirish Pande2012-04-1220-552/+7612
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154616 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch improves the MCJIT runtime dynamic loader by adding new handlingPreston Gurd2012-04-1228-81/+320
| | | | | | | | | | | | of zero-initialized sections, virtual sections and common symbols and preventing the loading of sections which are not required for execution such as debug information. Patch by Andy Kaylor! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154610 91177308-0d34-0410-b5e6-96231b3b80d8
* Generalize r153635 to deal with TokenFactor chains; also clean up the logic ↵Evan Cheng2012-04-121-41/+51
| | | | | | and fix the tests. rdar://11069732, rdar://11236106 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154604 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: enable assembler output through the MC layer.Evandro Menezes2012-04-1216-376/+685
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154597 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DFA generator for VLIW targets to ReleaseNotes.html and CREDITS.TXT.Anshuman Dasgupta2012-04-122-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154590 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove README entry obsoleted by register masks.Benjamin Kramer2012-04-121-16/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154588 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a remaining reference to the obsolete C backend in configureJean-Daniel Dupas2012-04-122-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154587 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix 128-bit ptest intrinsics to take v2i64 instead of v4f32 since these are ↵Craig Topper2012-04-124-25/+25
| | | | | | integer instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154580 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM 'adr' fixups don't need the interworking addend tweaking.Jim Grosbach2012-04-121-0/+3
| | | | | | | | They reference the PC directly, so things work properly that way. rdar://11231229 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154576 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert changes that were accidentally committed.Akira Hatanaka2012-04-111-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154563 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix string that is being checked.Akira Hatanaka2012-04-111-5/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154547 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user,Akira Hatanaka2012-04-113-3/+26
| | | | | | | | otherwise expand FNEG during legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154546 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user.Akira Hatanaka2012-04-114-0/+117
| | | | | | | | Invalid operation is signaled if the operand of these instructions is NaN. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154545 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a case of ARM disassembly getting an assert on a bad encodingKevin Enderby2012-04-112-0/+15
| | | | | | | of a VST instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154544 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bugs in lowering of FCOPYSIGN nodes.Akira Hatanaka2012-04-113-95/+183
| | | | | | | | | | | | - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154540 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove incorrect comment.Jim Grosbach2012-04-111-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154533 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Remove hard tab characters.Jim Grosbach2012-04-111-28/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154532 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Whitespace.Jim Grosbach2012-04-112-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154531 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pasto.Benjamin Kramer2012-04-111-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154527 91177308-0d34-0410-b5e6-96231b3b80d8
* Typo.Chad Rosier2012-04-111-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154522 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen's regpressure: emit per-registerclass weight limits.Andrew Trick2012-04-114-28/+47
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154518 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-113-2/+7
| | | | | | | | | | While there is an encoding for it in VUZP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11222366 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154511 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen'd regpressure: register unit set pruning.Andrew Trick2012-04-111-18/+14
| | | | | | | The pruning is more complete if it is not done incrementally. The code is also a tad less convluted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154510 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM 'vzip.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-113-2/+7
| | | | | | | | | | While there is an encoding for it in VZIP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11221911 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154505 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the build under Debian GNU/Hurd.Sylvestre Ledru2012-04-115-5/+20
| | | | | | | | Thanks to Pino Toscano for the patch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154500 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-02-13 07:32:47 +0000