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* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-38/+24
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-3/+3
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVectorEric Christopher2013-07-031-2/+2
| | | | | | to avoid specifying the vector size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185511 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r178845 with fix - Fix bug in PEI's virtual-register scavengingHal Finkel2013-04-051-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes PEI as previously described, but correctly handles the case where the instruction defining the virtual register to be scavenged is the first in the block. Arnold provided me with a bugpoint-reduced test case, but even that seems too large to use as a regression test. If I'm successful in cleaning it up then I'll commit that as well. Original commit message: This change fixes a bug that I introduced in r178058. After a register is scavenged using one of the available spills slots the instruction defining the virtual register needs to be moved to after the spill code. The scavenger has already processed the defining instruction so that registers killed by that instruction are available for definition in that same instruction. Unfortunately, after this, the scavenger needs to iterate through the spill code and then visit, again, the instruction that defines the now-scavenged register. In order to avoid confusion, the register scavenger needs the ability to 'back up' through the spill code so that it can again process the instructions in the appropriate order. Prior to this fix, once the scavenger reached the just-moved instruction, it would assert if it killed any registers because, having already processed the instruction, it believed they were undefined. Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar for diagnosing the problem and testing this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178919 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r178845 - Fix bug in PEI's virtual-register scavengingHal Finkel2013-04-051-17/+0
| | | | | | | | | | | | | | | | | | | | | | Reverting because this breaks one of the LTO builders. Original commit message: This change fixes a bug that I introduced in r178058. After a register is scavenged using one of the available spills slots the instruction defining the virtual register needs to be moved to after the spill code. The scavenger has already processed the defining instruction so that registers killed by that instruction are available for definition in that same instruction. Unfortunately, after this, the scavenger needs to iterate through the spill code and then visit, again, the instruction that defines the now-scavenged register. In order to avoid confusion, the register scavenger needs the ability to 'back up' through the spill code so that it can again process the instructions in the appropriate order. Prior to this fix, once the scavenger reached the just-moved instruction, it would assert if it killed any registers because, having already processed the instruction, it believed they were undefined. Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar for diagnosing the problem and testing this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178916 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug in PEI's virtual-register scavengingHal Finkel2013-04-051-0/+17
| | | | | | | | | | | | | | | | | | | | This change fixes a bug that I introduced in r178058. After a register is scavenged using one of the available spills slots the instruction defining the virtual register needs to be moved to after the spill code. The scavenger has already processed the defining instruction so that registers killed by that instruction are available for definition in that same instruction. Unfortunately, after this, the scavenger needs to iterate through the spill code and then visit, again, the instruction that defines the now-scavenged register. In order to avoid confusion, the register scavenger needs the ability to 'back up' through the spill code so that it can again process the instructions in the appropriate order. Prior to this fix, once the scavenger reached the just-moved instruction, it would assert if it killed any registers because, having already processed the instruction, it believed they were undefined. Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar for diagnosing the problem and testing this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178845 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the register scavenger for targets that provide custom spillingHal Finkel2013-03-261-2/+3
| | | | | | | | | | | As pointed out by Richard Sandiford, my recent updates to the register scavenger broke targets that use custom spilling (because the new code assumed that if there were no valid spill slots, than spilling would be impossible). I don't have a test case, but it should be possible to create one for Thumb 1, Mips 16, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178073 91177308-0d34-0410-b5e6-96231b3b80d8
* Update PEI's virtual-register-based scavenging to support multiple ↵Hal Finkel2013-03-261-2/+5
| | | | | | | | | | | | | | | | | | | simultaneous mappings The previous algorithm could not deal properly with scavenging multiple virtual registers because it kept only one live virtual -> physical mapping (and iterated through operands in order). Now we don't maintain a current mapping, but rather use replaceRegWith to completely remove the virtual register as soon as the mapping is established. In order to allow the register scavenger to return a physical register killed by an instruction for definition by that same instruction, we now call RS->forward(I) prior to eliminating virtual registers defined in I. This requires a minor update to forward to ignore virtual registers. These new features will be tested in forthcoming commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178058 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow the register scavenger to spill multiple registersHal Finkel2013-03-221-15/+37
| | | | | | | | | | | | | | | | | | This patch lets the register scavenger make use of multiple spill slots in order to guarantee that it will be able to provide multiple registers simultaneously. To support this, the RS's API has changed slightly: setScavengingFrameIndex / getScavengingFrameIndex have been replaced by addScavengingFrameIndex / isScavengingFrameIndex / getScavengingFrameIndices. In forthcoming commits, the PowerPC backend will use this capability in order to implement the spilling of condition registers, and some special-purpose registers, without relying on r0 being reserved. In some cases, spilling these registers requires two GPRs: one for addressing and one to hold the value being transferred. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove ScavengedRC from RegisterScavengingHal Finkel2013-03-221-5/+1
| | | | | | | ScavengedRC was a dead private variable (set, but not otherwise used). No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177708 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix include guards so they exactly match file names.Jakub Staszak2013-01-101-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172025 91177308-0d34-0410-b5e6-96231b3b80d8
* Sort the #include lines for the include/... tree with the script.Chandler Carruth2012-12-031-1/+1
| | | | | | | | | | AKA: Recompile *ALL* the source code! This one went much better. No manual edits here. I spot-checked for silliness and grep-checked for really broken edits and everything seemed good. It all still compiles. Yell if you see something that looks goofy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169133 91177308-0d34-0410-b5e6-96231b3b80d8
* [reg scavenger] Fix the isUsed/isAliasUsed functions so as to not report a falseChad Rosier2012-11-151-3/+5
| | | | | | | | | | | | | | | | | positive. In this particular case, R6 was being spilled by the register scavenger when it was in fact dead. The isUsed function reported R6 as used because the R6_R7 alias was reserved (due to the fact that we've reserved R7 as the FP). The solution is to only check if the original register (i.e., R6) isReserved and not the aliases. The aliases are only checked to make sure they're available. The test case is derived from one of the nightly tester benchmarks and is rather intractable and difficult to reproduce, so I haven't included it. rdar://12592448 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168054 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen2012-10-151-6/+3
| | | | | | | Using the cached bit vector in MRI avoids comstantly allocating and recomputing the reserved register bit vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165983 91177308-0d34-0410-b5e6-96231b3b80d8
* Track reserved registers separately from RegsAvailable.Jakob Stoklund Olesen2012-02-231-2/+3
| | | | | | | The bulk masking operations from register mask operands don't account for reserved registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151222 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some scavenger performance issues.Jakob Stoklund Olesen2012-01-291-4/+5
| | | | | | | | | | | | | - Don't call malloc+free in the very hot forward(). - Don't call isTiedToDefOperand(). - Don't create BitVector temporaries. - Merge DeadRegs into KillRegs. - Eliminate the early clobber checks, they were irrelevant to scavenging. - Remove unnecessary code from -Asserts builds. This speeds up ARM PEI by 3.4x and overall llc -O0 codegen time by 11%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149189 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the register scavenger to take subregs into account when finding a ↵Jim Grosbach2011-03-051-1/+1
| | | | | | free register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127049 91177308-0d34-0410-b5e6-96231b3b80d8
* After r107880, findSurvivorReg() no longer needs to be public.Jim Grosbach2010-07-081-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107887 91177308-0d34-0410-b5e6-96231b3b80d8
* When processing frame index virtual registers, consider all available registersJim Grosbach2010-07-081-5/+14
| | | | | | | | | | (if there are any) and use the one which remains available for the longest rather than just using the first one. This should help enable better re-use of the loaded frame index values. rdar://7318760 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107847 91177308-0d34-0410-b5e6-96231b3b80d8
* Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach2009-10-071-1/+3
| | | | | | | | | | | | | | | | | | | | | | a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct comment pastoJim Grosbach2009-09-151-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81896 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify RegScavenger::FindUnusedReg.Jakob Stoklund Olesen2009-08-181-8/+2
| | | | | | | | | - Drop the Candidates argument and fix all callers. Now that RegScavenger tracks available registers accurately, there is no need to restict the search. - Make sure that no aliases of the found register are in use. This was a potential bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79369 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace RegScavenger::DistanceMap with a simpler local algorithm.Jakob Stoklund Olesen2009-08-161-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79195 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up the public interface of RegScavenger.Jakob Stoklund Olesen2009-08-161-25/+20
| | | | | | Remove unused methods and make others private. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79194 91177308-0d34-0410-b5e6-96231b3b80d8
* Rebuild RegScavenger::DistanceMap each time it is needed.Jakob Stoklund Olesen2009-08-111-13/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The register scavenger maintains a DistanceMap that maps MI pointers to their distance from the top of the current MBB. The DistanceMap is built incrementally in forward() and in bulk in findFirstUse(). It is used by scavengeRegister() to determine which candidate register has the longest unused interval. Unfortunately the DistanceMap contents can become outdated. The first time scavengeRegister() is called, the DistanceMap is filled to cover the MBB. If then instructions are inserted in the MBB (as they always are following scavengeRegister()), the recorded distances are too short. This causes bad behaviour in the included test case where a register use /after/ the current position is ignored because findFirstUse() thinks is is /before/ the current position. A "using an undefined register" assertion follows promptly. The fix is to build a fresh DistanceMap at the top of scavengeRegister(), and discard it after use. This means that DistanceMap is no longer needed as a RegScavenger member variable, and forward() doesn't need to update it. The fix then discloses issue number two in the same test case: The candidate search in scavengeRegister() finds a CSR that has been saved in the prologue, but is currently unused. It would be both inefficient and wrong to spill such a register in the emergency spill slot. In the present case, the emergency slot restore is placed immediately before the normal epilogue restore, leading to a "Redefining a live register" assertion. Fix number two: When scavengerRegister() stumbles upon an unused register that is overwritten later in the MBB, return that register early. It is important to verify that the register is defined later in the MBB, otherwise it might be an unspilled CSR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78650 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove RegisterScavenger::isSuperRegUsed(). This completely reverses the ↵Jakob Stoklund Olesen2009-08-081-3/+0
| | | | | | | | | | | | | | | | mistaken commit r77904. Now there is no special treatment of instructions that redefine part of a super-register. Instead, the super-register is marked with <imp-use,kill> and <imp-def>. For instance, from LowerSubregs on ARM: subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1<undef>, %D1<kill>, 5 subreg: %D2<def> = FCPYD %D1<kill>, 14, %reg0, %Q1<imp-def> subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1, %D0<kill>, 6 subreg: %D3<def> = FCPYD %D0<kill>, 14, %reg0, %Q1<imp-use,kill>, %Q1<imp-def> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78466 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify RegScavenger::forward a bit more.Jakob Stoklund Olesen2009-08-081-1/+7
| | | | | | | | | | | Verify that early clobber registers and their aliases are not used. All changes to RegsAvailable are now done as a transaction so the order of operands makes no difference. The included test case is from PR4686. It has behaviour that was dependent on the order of operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78465 91177308-0d34-0410-b5e6-96231b3b80d8
* Get rid of RegScavenger::backwards() before the bitrot spreads.Jakob Stoklund Olesen2009-08-061-8/+3
| | | | | | If we need it one day, there is nothing wrong with putting it back in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78337 91177308-0d34-0410-b5e6-96231b3b80d8
* Reg Scavenging generalization (Thumb support):John Mosby2009-08-061-0/+4
| | | | | | | | - start support for new PEI w/reg alloc, allow running RS from emit{Pro,Epi}logue() target hooks. - fix minor issue with recursion detection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78318 91177308-0d34-0410-b5e6-96231b3b80d8
* Scavenger asserts.Jakob Stoklund Olesen2009-08-021-0/+3
| | | | | | | Allow imp-def and imp-use of anything in the scavenger asserts, just like the machine code verifier. Allow redefinition of a sub-register of a live register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77904 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove special handling of implicit_def. Fix a couple more bugs in ↵Evan Cheng2009-07-011-13/+2
| | | | | | | | | liveintervalanalysis and coalescer handling of implicit_def. Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74601 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily restore the scavenger implicit_def checking code. MachineOperand ↵Evan Cheng2009-06-301-2/+13
| | | | | | isUndef mark is not being put on implicit_def of physical registers (created for parameter passing, etc.). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74519 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a bit IsUndef to MachineOperand. This indicates the def / use register ↵Evan Cheng2009-06-301-13/+2
| | | | | | | | | | | operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing. This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74518 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't pass BitVectors by value, pass them by reference.Roman Levenstein2009-02-061-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63931 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix RegScavenger::forward() to work on basic blocks containing exactlyDan Gohman2008-12-191-0/+1
| | | | | | | one instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61236 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete the RegScavenging constructor that takes a MachineBasicBlockDan Gohman2008-12-191-4/+0
| | | | | | | | argument. Nothing was using it, and it set the MBB member without calling enterBasicBlock, which was problematic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61234 91177308-0d34-0410-b5e6-96231b3b80d8
* - Register scavenger should use MachineRegisterInfo and internal map to find ↵Evan Cheng2008-11-201-12/+28
| | | | | | | | | | the first use of a register after a given machine instruction. - When scavenging a register, in addition to the spill, insert a restore before the first use. - Abort if client is looking to scavenge a register even when a previously scavenged register is still live. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59697 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow registers defined by implicit_def to be clobbered.Evan Cheng2008-04-101-3/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49512 91177308-0d34-0410-b5e6-96231b3b80d8
* Forgot this.Evan Cheng2008-04-051-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49247 91177308-0d34-0410-b5e6-96231b3b80d8
* When setting the "unused" info, take into account something like this:Bill Wendling2008-03-061-1/+1
| | | | | | | | | %r3<def> = OR %x3<kill>, %x3 We don't want to mark the %r3 as unused even though it's a sub-register of %x3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48003 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor code. Remove duplicated functions that basically do the same thing asEvan Cheng2008-03-051-1/+1
| | | | | | | findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47927 91177308-0d34-0410-b5e6-96231b3b80d8
* This is the initial check-in for adding register scavenging to PPC. (Currently,Bill Wendling2008-03-031-2/+2
| | | | | | | | | | | PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that it uses a register other than the default R0 register (the scavenger scrounges for one). A significant part of this patch fixes how kill information is handled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47863 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't attribute in file headers anymore. See llvmdev for theChris Lattner2007-12-291-2/+2
| | | | | | | | discussion of this change. Boy are my fingers tired. ;-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45411 91177308-0d34-0410-b5e6-96231b3b80d8
* Add explicit keywords and remove spurious trailing semicolons.Dan Gohman2007-08-271-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41482 91177308-0d34-0410-b5e6-96231b3b80d8
* Add explicit keywords.Dan Gohman2007-07-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37925 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass call frame setup SP adjustment along to eliminateFrameIndex().Evan Cheng2007-05-011-5/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36624 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable toDale Johannesen2007-03-261-8/+8
| | | | | | | hopefully forestall similar errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35362 91177308-0d34-0410-b5e6-96231b3b80d8
* maintain LiveIn when splitting blocks (register scavenging needs it)Dale Johannesen2007-03-201-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35226 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment.Evan Cheng2007-03-181-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35139 91177308-0d34-0410-b5e6-96231b3b80d8
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