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path: root/include/llvm/CodeGen/TargetSchedule.h
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* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-1/+2
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-3/+3
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Update to LLVM 3.5a.Stephen Hines2014-04-241-1/+9
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-301-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will use be able the new schedule module for instruction latencies in the if-converter (the logic is such that if there is no itineary we will use the new sched model for the latencies). Before, we queried "TTI->getInstructionLatency()" for the instruction latency and the extra prediction cost. Now, we query the TargetSchedule abstraction for the instruction latency and TargetInstrInfo for the extra predictation cost. The TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if an itinerary exists, otherwise it will use the new schedule model. ATTENTION: Out of tree targets! (I will also send out an email later to LLVMDev) This means, if your target implements unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost); and returns a value for "PredCost", you now also need to implement unsigned getPredictationCost(const MachineInstr *MI); (if your target uses the IfConversion.cpp pass) radar://15077010 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191671 91177308-0d34-0410-b5e6-96231b3b80d8
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-151-16/+12
| | | | | | | | | | | | | Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix include guards so they exactly match file names.Jakub Staszak2013-01-101-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172025 91177308-0d34-0410-b5e6-96231b3b80d8
* MIsched: add an ILP window property to machine model.Andrew Trick2013-01-091-0/+3
| | | | | | | | | | This was an experimental option, but needs to be defined per-target. e.g. PPC A2 needs to aggressively hide latency. I converted some in-order scheduling tests to A2. Hal is working on more test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
* Sort the #include lines for the include/... tree with the script.Chandler Carruth2012-12-031-3/+3
| | | | | | | | | | AKA: Recompile *ALL* the source code! This one went much better. No manual edits here. I spot-checked for silliness and grep-checked for really broken edits and everything seemed good. It all still compiles. Yell if you see something that looks goofy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169133 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: TargetSchedule interface for machine resources.Andrew Trick2012-11-061-5/+51
| | | | | | | | | | | Expose the processor resources defined by the machine model to the scheduler and other clients through the TargetSchedule interface. Normalize each resource count with respect to other kinds of resources. This allows scheduling heuristics to balance resources against other kinds of resources and latency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167444 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-101-4/+22
| | | | | | | | Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165603 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Add computeInstrLatency to TargetSchedModel.Andrew Trick2012-10-091-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165566 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Doxument the TargetSchedule API.Andrew Trick2012-10-091-7/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165565 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for ↵Andrew Trick2012-10-091-2/+2
| | | | | | external users of TargetSchedule. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165564 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch MachineTraceMetrics to the new TargetSchedModel interface.Jakob Stoklund Olesen2012-10-041-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165235 91177308-0d34-0410-b5e6-96231b3b80d8
* TargetSchedModel API. Implement latency lookup, disabled.Andrew Trick2012-09-181-6/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164098 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-171-22/+6
| | | | | | | | I have to work out the Target/CodeGen header dependencies before putting this back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
* TargetSchedModel API. Implement latency lookup, disabled.Andrew Trick2012-09-171-6/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164065 91177308-0d34-0410-b5e6-96231b3b80d8
* comment typoAndrew Trick2012-09-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163935 91177308-0d34-0410-b5e6-96231b3b80d8
* TargetSchedModel interface. To be implemented...Andrew Trick2012-09-141-0/+63
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163934 91177308-0d34-0410-b5e6-96231b3b80d8
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