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* Add DwarfWriter interface to mainipulate source location info.Devang Patel2009-01-121-0/+20
| | | | | | | ( May be this info should be directly handled by the dwarf writer ? ) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62096 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR3241: Currently EmitCopyFromReg emits a copy from the physical ↵Evan Cheng2009-01-121-1/+1
| | | | | | | | | register to a virtual register unless it requires an expensive cross class copy. That means we are only treating "expensive to copy" register dependency as physical register dependency. Also future proof the scheduler to handle "normal" physical register dependencies. The code is not exercised yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62074 91177308-0d34-0410-b5e6-96231b3b80d8
* Duplicated node may produce a non-physical register def.Evan Cheng2009-01-091-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62015 91177308-0d34-0410-b5e6-96231b3b80d8
* Request DwarfWriter. This will be used to handle dbg_* intrinsics.Devang Patel2009-01-091-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61999 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert DwarfWriter into a pass.Devang Patel2009-01-081-7/+8
| | | | | | | Now Users request DwarfWriter through getAnalysisUsage() instead of creating an instance of DwarfWriter object directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61955 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete unnecessary parens around return values.Dan Gohman2009-01-081-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61950 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct the form of the atomic opcode names in a comment.Dan Gohman2009-01-081-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61947 91177308-0d34-0410-b5e6-96231b3b80d8
* Add empty() methods for register def lists.Dan Gohman2009-01-071-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61890 91177308-0d34-0410-b5e6-96231b3b80d8
* The coalescer does not coalesce a virtual register to a physical register if ↵Evan Cheng2009-01-071-0/+7
| | | | | | | | | | | | | | | any of the physical register's sub-register live intervals overlaps with the virtual register. This is overly conservative. It prevents a extract_subreg from being coalesced away: v1024 = EDI // not killed = = EDI One possible solution is for the coalescer to examine the sub-register live intervals in the same manner as the physical register. Another possibility is to examine defs and uses (when needed) of sub-registers. Both solutions are too expensive. For now, look for "short virtual intervals" and scan instructions to look for conflict instead. This is a small win on x86-64. e.g. It shaves 403.gcc by ~80 instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61847 91177308-0d34-0410-b5e6-96231b3b80d8
* TargetLowering.h #includes SelectionDAGNodes.h, so it doesn't need itsDan Gohman2009-01-051-2/+0
| | | | | | | | own OpActionsCapacity magic number; it can just use ISD::BUILTIN_OP_END, as long as it takes care to round up when needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61733 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up #includes, deleting a bunch of unnecessary #includes.Dan Gohman2009-01-0517-53/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the code from the scheduler that commuted two-addressDan Gohman2009-01-031-3/+0
| | | | | | | | | | | | | | | instructions to avoid copies, because TwoAddressInstructionPass also does this optimization. The scheduler's version didn't account for live-out values, which resulted in spurious commutes and missed opportunities. Now, TwoAddressInstructionPass handles all the opportunities, instead of just those that the scheduler missed. The result is usually the same, though there are occasional trivial differences resulting from the avoidance of spurious commutes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61611 91177308-0d34-0410-b5e6-96231b3b80d8
* Some compilers are picky about accessing the first element of a std::vector ifBill Wendling2009-01-011-2/+5
| | | | | | | there's nothing in the vector. Pacify them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61536 91177308-0d34-0410-b5e6-96231b3b80d8
* Forgot to commit this file.Owen Anderson2008-12-281-0/+10
| | | | | | | Add a clear() method to remove all ranges and value numbers for a live interval. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61459 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up the atomic opcodes in SelectionDAG.Dan Gohman2008-12-232-158/+45
| | | | | | | | | | | | | | This removes all the _8, _16, _32, and _64 opcodes and replaces each group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode is now used to carry the size information. In tablegen, the size-specific opcodes are replaced by size-independent opcodes that utilize the ability to compose them with predicates. This shrinks the per-opcode tables and makes the code that handles atomics much more concise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61389 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename BuildSchedUnits to BuildSchedGraph, and refactor theDan Gohman2008-12-233-8/+13
| | | | | | | code in ScheduleDAGSDNodes' BuildSchedGraph into separate functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61376 91177308-0d34-0410-b5e6-96231b3b80d8
* Comment MO_FPImmediate and doxygenate surrounding comments.Dan Gohman2008-12-231-9/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61374 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor a bunch of code out of AsmPrinter::EmitGlobalConstant into separateDan Gohman2008-12-221-0/+8
| | | | | | | functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61345 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an assertion to the ScheduleDAGInstrs class to catch SUnitsDan Gohman2008-12-221-0/+4
| | | | | | | | reallocations. We don't do cloning on MachineInstr schedule DAGs, but this is a worthwhile sanity check regardless. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61343 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an accesor for the isNormalMemory field in the SDep class.Dan Gohman2008-12-221-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61342 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an assertion to catch SUnits reallocations. And add a doxygenDan Gohman2008-12-221-0/+18
| | | | | | | comment for the ScheduleDAGSDNodes class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61341 91177308-0d34-0410-b5e6-96231b3b80d8
* LiveInterval::removeKills and isKill don't need 'this' andDan Gohman2008-12-201-2/+2
| | | | | | | can be static member functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61278 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR3149. If an early clobber def is a physical register and it is tied to ↵Evan Cheng2008-12-191-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | an input operand, it effectively extends the live range of the physical register. Currently we do not have a good way to represent this. 172 %ECX<def> = MOV32rr %reg1039<kill> 180 INLINEASM <es:subl $5,$1 sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9, %EAX<kill>, 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0 188 %EAX<def> = MOV32rr %EAX<kill> 196 %ECX<def> = MOV32rr %ECX<kill> 204 %ECX<def> = MOV32rr %ECX<kill> 212 %EAX<def> = MOV32rr %EAX<kill> 220 %EAX<def> = MOV32rr %EAX 228 %reg1039<def> = MOV32rr %ECX<kill> The early clobber operand ties ECX input to the ECX def. The live interval of ECX is represented as this: %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47) The right way to represent this is something like %reg20,inf = [46,47:2)[174,182:1)[181:230:0) 0@174-(182) 1@181-230 @2@46-(47) Of course that won't work since that means overlapping live ranges defined by two val#. The workaround for now is to add a bit to val# which says the val# is redefined by a early clobber def somewhere. This prevents the move at 228 from being optimized away by SimpleRegisterCoalescing::AdjustCopiesBackFrom. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61259 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix RegScavenger::forward() to work on basic blocks containing exactlyDan Gohman2008-12-191-0/+1
| | | | | | | one instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61236 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete the RegScavenging constructor that takes a MachineBasicBlockDan Gohman2008-12-191-4/+0
| | | | | | | | argument. Nothing was using it, and it set the MBB member without calling enterBasicBlock, which was problematic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61234 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support for vector widening.Mon P Wang2008-12-182-35/+72
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61209 91177308-0d34-0410-b5e6-96231b3b80d8
* Today the front-ends (llvm-gcc and clang) generate multiple ↵Devang Patel2008-12-171-1/+2
| | | | | | | | | | llvm.dbg.compile_units to identify source file for various debug entities. Each llvm.dbg.compile_unit matches one file on the disk. However, the backend only supports one DW_TAG_compile_unit per .o file. The backend selects first compile_unit from the vector to construct DW_TAG_compile_unit entry, which is not correct in all cases. First step to resolve this is, record file name and directory directly in debug info for various debug entities. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61164 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the comments for getDepth and getHeight.Dan Gohman2008-12-171-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61120 91177308-0d34-0410-b5e6-96231b3b80d8
* Add initial support for back-scheduling address computations,Dan Gohman2008-12-161-2/+3
| | | | | | | | especially in the case of addresses computed from loop induction variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61075 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some register-alias-related bugs in the post-RA scheduler livenessDan Gohman2008-12-163-28/+68
| | | | | | | | | | | | | | | computation code. Also, avoid adding output-depenency edges when both defs are dead, which frequently happens with EFLAGS defs. Compute Depth and Height lazily, and always in terms of edge latency values. For the schedulers that don't care about latency, edge latencies are set to 1. Eliminate Cycle and CycleBound, and LatencyPriorityQueue's Latencies array. These are all subsumed by the Depth and Height fields. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61073 91177308-0d34-0410-b5e6-96231b3b80d8
* Move addPred and removePred out-of-line.Dan Gohman2008-12-161-53/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61067 91177308-0d34-0410-b5e6-96231b3b80d8
* Make addPred and removePred return void, since the return value is notDan Gohman2008-12-161-9/+6
| | | | | | | currently used by anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61066 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a getSDep() access function to SUnitIterator to return theDan Gohman2008-12-161-2/+5
| | | | | | | current SDep. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61064 91177308-0d34-0410-b5e6-96231b3b80d8
* Reorder some SDep methods. No functionality change.Dan Gohman2008-12-161-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61063 91177308-0d34-0410-b5e6-96231b3b80d8
* SDep's operator== should compare the Latency field too.Dan Gohman2008-12-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61062 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r60997, this time without forgetting thatDuncan Sands2008-12-141-1/+1
| | | | | | | | target constants are allowed to have an illegal type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61006 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert r60997. It was causing this failure:Bill Wendling2008-12-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | Running /Users/void/llvm/llvm.src/test/CodeGen/Generic/dg.exp ... FAIL: /Users/void/llvm/llvm.src/test/CodeGen/Generic/asm-large-immediate.ll Failed with exit(1) at line 1 while running: llvm-as < /Users/void/llvm/llvm.src/test/CodeGen/Generic/asm-large-immediate.ll | llc | /usr/bin/grep 68719476738 Assertion failed: ((TypesNeedLegalizing || getTypeAction(VT) == Legal) && "Illegal type introduced after type legalization?"), function HandleOp, file /Users/void/llvm/llvm.src/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp, line 493. 0 llc 0x0085392e char const* std::find<char const*, char>(char const*, char const*, char const&) + 98 1 llc 0x00853e63 llvm::sys::PrintStackTraceOnErrorSignal() + 593 2 libSystem.B.dylib 0x96cac09b _sigtramp + 43 3 libSystem.B.dylib 0xffffffff _sigtramp + 1765097359 4 libSystem.B.dylib 0x96d24ec2 raise + 26 5 libSystem.B.dylib 0x96d3447f abort + 73 6 libSystem.B.dylib 0x96d26063 __assert_rtn + 101 7 llc 0x004f9018 llvm::cast_retty<llvm::SubprogramDesc, llvm::DebugInfoDesc*>::ret_type llvm::cast<llvm::Sub ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61001 91177308-0d34-0410-b5e6-96231b3b80d8
* LegalizeDAG is not supposed to introduce illegalDuncan Sands2008-12-131-1/+1
| | | | | | | | types into the DAG if they were not already there. Check this with an assertion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60997 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix MachineCodeEmitter to use uintptr_t instead of intptr_t. This avoids ↵Evan Cheng2008-12-102-31/+36
| | | | | | some overflow issues. Patch by Thomas Jablin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60828 91177308-0d34-0410-b5e6-96231b3b80d8
* Update CalcLatency to work in terms of edge latencies, rather thanDan Gohman2008-12-101-1/+1
| | | | | | | | | node latencies. Use CalcLatency instead of manual code in CalculatePriorities to keep it consistent. Previously it computed slightly different results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60817 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a couple of Dwarf bugs.Evan Cheng2008-12-101-1/+8
| | | | | | | | - Emit DW_AT_byte_size for struct and union of size zero. - Emit DW_AT_declaration for forward type declaration. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60812 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite the SDep class, and simplify some of the related code.Dan Gohman2008-12-093-73/+208
| | | | | | | | | | | | | | | | | | The Cost field is removed. It was only being used in a very limited way, to indicate when the scheduler should attempt to protect a live register, and it isn't really needed to do that. If we ever want the scheduler to start inserting copies in non-prohibitive situations, we'll have to rethink some things anyway. A Latency field is added. Instead of giving each node a single fixed latency, each edge can have its own latency. This will eventually be used to model various micro-architecture properties more accurately. The PointerIntPair class and an internal union are now used, which reduce the overall size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60806 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sub/mul overflow intrinsics. This currently doesn't have aBill Wendling2008-12-091-0/+6
| | | | | | | | target-independent way of determining overflow on multiplication. It's very tricky. Patch by Zoltan Varga! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60800 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR3117: not all nodes being legalized. TheDuncan Sands2008-12-091-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | essential problem was that the DAG can contain random unused nodes which were never analyzed. When remapping a value of a node being processed, such a node may become used and need to be analyzed; however due to operands being transformed during analysis the node may morph into a different one. Users of the morphing node need to be updated, and this wasn't happening. While there I added a bunch of documentation and sanity checks, so I (or some other poor soul) won't have to scratch their head over this stuff so long trying to remember how it was all supposed to work next time some obscure problem pops up! The extra sanity checking exposed a few places where invariants weren't being preserved, so those are fixed too. Since some of the sanity checking is expensive, I added a flag to turn it on. It is also turned on when building with ENABLE_EXPENSIVE_CHECKS=1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60797 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment typo.Duncan Sands2008-12-081-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60698 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor out the code for sign-extending/truncating gep indicesDan Gohman2008-12-081-0/+5
| | | | | | | | | | and use it in x86 address mode folding. Also, make getRegForValue return 0 for illegal types even if it has a ValueMap for them, because Argument values are put in the ValueMap. This fixes PR3181. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60696 91177308-0d34-0410-b5e6-96231b3b80d8
* Move createVirtualRegister out-of-line.Dan Gohman2008-12-081-13/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60684 91177308-0d34-0410-b5e6-96231b3b80d8
* Drop the reg argument to isRegReDefinedByTwoAddr, which was redundant.Dan Gohman2008-12-051-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60586 91177308-0d34-0410-b5e6-96231b3b80d8
* Have PseudoSourceValue override Value::dump, so that it worksDan Gohman2008-12-031-0/+6
| | | | | | | | on PseudoSourceValue values. This also fixes a FIXME in lib/VMCode/AsmWriter.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60507 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend X86's addFrameReference to add a MachineMemOperand forDan Gohman2008-12-032-3/+8
| | | | | | | | the frame reference. This will help post-RA scheduling determine that spills to distinct stack slots are independent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60486 91177308-0d34-0410-b5e6-96231b3b80d8
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