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| * LiveRegUnits: Use *MBB for consistency and convenience.Andrew Trick2013-10-141-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192634 91177308-0d34-0410-b5e6-96231b3b80d8
| * Use a SparseSet in LiveRegUnits.Andrew Trick2013-10-141-7/+13
| | | | | | | | | | | | | | | | | | | | Some clients may add block live ins and may track liveness over a large scope. This guarantees an efficient implementation in all cases with no memory allocation/deallocation, independent of the number of target registers. It could be slightly less convenient but is fine in the expected case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192622 91177308-0d34-0410-b5e6-96231b3b80d8
| * Move LiveRegUnits implementation into .cpp. Comment and format.Andrew Trick2013-10-141-87/+13
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192621 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove extra indentation in LiveRegUnits.Andrew Trick2013-10-141-112/+112
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192620 91177308-0d34-0410-b5e6-96231b3b80d8
| * Convert LiveRegUnits methods to the current convention (it's new code).Andrew Trick2013-10-141-15/+15
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192619 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove the now unused strong phi elimination pass.Rafael Espindola2013-10-141-8/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192604 91177308-0d34-0410-b5e6-96231b3b80d8
| * Introduce ad hoc liveness tracking utility: LiveRegUnitsMatthias Braun2013-10-111-0/+156
| | | | | | | | | | | | | | Contains a set of live register (units) and code to move forward and backward in the schedule while updating the live set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192481 91177308-0d34-0410-b5e6-96231b3b80d8
| * Make AsmPrinter::emitImplicitDef a virtual method so targets can emit custom ↵Justin Holewinski2013-10-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | comments for implicit defs For NVPTX, this fixes a crash where the emitImplicitDef implementation was expecting physical registers, while NVPTX uses virtual registers (with a couple of exceptions). Now, the implicit def comment will be emitted as a true PTX register name. Other targets can use this to customize the output of implicit def comments. Fixes PR17519 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192444 91177308-0d34-0410-b5e6-96231b3b80d8
| * Print register in LiveInterval::print()Matthias Braun2013-10-101-0/+5
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192398 91177308-0d34-0410-b5e6-96231b3b80d8
| * Represent RegUnit liveness with LiveRange instanceMatthias Braun2013-10-102-16/+16
| | | | | | | | | | | | | | Previously LiveInterval has been used, but having a spill weight and register number is unnecessary for a register unit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192397 91177308-0d34-0410-b5e6-96231b3b80d8
| * Work on LiveRange instead of LiveInterval where possibleMatthias Braun2013-10-101-5/+5
| | | | | | | | | | | | | | Also change some pointer arguments to references at some places where 0-pointers are not allowed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192396 91177308-0d34-0410-b5e6-96231b3b80d8
| * Pass LiveQueryResult by valueMatthias Braun2013-10-101-96/+101
| | | | | | | | | | | | | | This makes the API a bit more natural to use and makes it easier to make LiveRanges implementation details private. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192394 91177308-0d34-0410-b5e6-96231b3b80d8
| * Refactor LiveInterval: introduce new LiveRange classMatthias Braun2013-10-102-101/+126
| | | | | | | | | | | | | | | | | | | | LiveRange just manages a list of segments and a list of value numbers now as LiveInterval did previously, but without having details like spill weight or a fixed register number. LiveInterval is now a subclass of LiveRange and simply adds the spill weight and the register number. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192393 91177308-0d34-0410-b5e6-96231b3b80d8
| * Rename LiveRange to LiveInterval::SegmentMatthias Braun2013-10-103-129/+124
| | | | | | | | | | | | | | | | The Segment struct contains a single interval; multiple instances of this struct are used to construct a live range, but the struct is not a live range by itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192392 91177308-0d34-0410-b5e6-96231b3b80d8
| * Rename parameter: defined regs are not incoming.Matthias Braun2013-10-101-3/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192391 91177308-0d34-0410-b5e6-96231b3b80d8
| * Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192361 91177308-0d34-0410-b5e6-96231b3b80d8
| * Revert "Implement AArch64 vector load/store multiple N-element structure ↵Rafael Espindola2013-10-101-1/+1
| | | | | | | | | | | | | | | | class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)." This reverts commit r192352. It broke the build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192354 91177308-0d34-0410-b5e6-96231b3b80d8
| * Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192352 91177308-0d34-0410-b5e6-96231b3b80d8
| * Explicitly request unsigned enum types when desiredReid Kleckner2013-10-081-1/+1
| | | | | | | | | | | | | | This fixes repeated -Wmicrosoft warnings when self-hosting clang on Windows, and gets us real unsigned enum types with MSVC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192227 91177308-0d34-0410-b5e6-96231b3b80d8
| * Implement aarch64 neon instruction set AdvSIMD (Across).Jiangning Liu2013-10-051-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192028 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences ↵Craig Topper2013-10-051-0/+2
| | | | | | | | | | | | of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192026 91177308-0d34-0410-b5e6-96231b3b80d8
| * Revert r191940 to see if it fixes the build bots.Craig Topper2013-10-041-2/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191941 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences ↵Craig Topper2013-10-041-0/+2
| | | | | | | | | | | | of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191940 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add v4f16 to supported value types.Pete Cooper2013-10-032-29/+35
| | | | | | | | | | | | | | This is useful for some ARM intrinsics such as VCVTN which does a <4 x float> <-> <4 x half> conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191870 91177308-0d34-0410-b5e6-96231b3b80d8
| * IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-301-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will use be able the new schedule module for instruction latencies in the if-converter (the logic is such that if there is no itineary we will use the new sched model for the latencies). Before, we queried "TTI->getInstructionLatency()" for the instruction latency and the extra prediction cost. Now, we query the TargetSchedule abstraction for the instruction latency and TargetInstrInfo for the extra predictation cost. The TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if an itinerary exists, otherwise it will use the new schedule model. ATTENTION: Out of tree targets! (I will also send out an email later to LLVMDev) This means, if your target implements unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost); and returns a value for "PredCost", you now also need to implement unsigned getPredictationCost(const MachineInstr *MI); (if your target uses the IfConversion.cpp pass) radar://15077010 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191671 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove an old workaround for a compiler that EOL'd years ago.Benjamin Kramer2013-09-291-6/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191643 91177308-0d34-0410-b5e6-96231b3b80d8
| * Allocate AtomicSDNode operands in SelectionDAG's allocator to stop leakage.Benjamin Kramer2013-09-291-10/+7
| | | | | | | | | | | | | | SDNode destructors are never called. As an optimization use AtomicSDNode's internal storage if we have a small number of operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191636 91177308-0d34-0410-b5e6-96231b3b80d8
| * Even more spelling fixes for "instruction".Robert Wilhelm2013-09-283-4/+4
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191611 91177308-0d34-0410-b5e6-96231b3b80d8
| * [stackprotector] Refactor the StackProtector pass from a single .cpp file ↵Josh Magee2013-09-271-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into StackProtector.h and StackProtector.cpp. No functionality change. Future patches will add analysis which will be used in other passes (PEI, StackSlot). The end goal is to support ssp-strong stack layout rules. WIP. Differential Revision: http://llvm-reviews.chandlerc.com/D1521 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191570 91177308-0d34-0410-b5e6-96231b3b80d8
| * [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-263-4/+30
| | | | | | | | | | | | | | Patch by Artyom Skrobov. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191428 91177308-0d34-0410-b5e6-96231b3b80d8
| * Initial support for Neon scalar instructions.Jiangning Liu2013-09-242-73/+91
| | | | | | | | | | | | | | | | | | | | | | | | Patch by Ana Pazos. 1.Added support for v1ix and v1fx types. 2.Added Scalar Pairwise Reduce instructions. 3.Added initial implementation of Scalar Arithmetic instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191263 91177308-0d34-0410-b5e6-96231b3b80d8
| * Allow subtarget selection of the default MachineScheduler and document the ↵Andrew Trick2013-09-202-14/+71
| | | | | | | | | | | | | | | | | | | | | | interface. The global registry is used to allow command line override of the scheduler selection, but does not work well as the normal selection API. For example, the same LLVM process should be able to target multiple targets or subtargets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191071 91177308-0d34-0410-b5e6-96231b3b80d8
| * simplify expressionAdrian Prantl2013-09-171-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190826 91177308-0d34-0410-b5e6-96231b3b80d8
| * Debug info: Fix PR16736 and rdar://problem/14990587.Adrian Prantl2013-09-161-0/+7
| | | | | | | | | | | | | | A DBG_VALUE is register-indirect iff the first operand is a register _and_ the second operand is an immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190821 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
| * white spaces and long linesJack Carter2013-09-091-30/+42
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190358 91177308-0d34-0410-b5e6-96231b3b80d8
| * mi-sched: cleanup register pressure update, remove a FIXME.Andrew Trick2013-09-062-1/+6
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190181 91177308-0d34-0410-b5e6-96231b3b80d8
| * Added MachineSchedPolicy.Andrew Trick2013-09-061-2/+26
| | | | | | | | | | | | | | | | Allow subtargets to customize the generic scheduling strategy. This is convenient for targets that don't need to add new heuristics by specializing the strategy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190176 91177308-0d34-0410-b5e6-96231b3b80d8
| * avoid unnecessary direct access to LiveInterval::rangesMatthias Braun2013-09-061-3/+7
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190170 91177308-0d34-0410-b5e6-96231b3b80d8
| * remove unused argument from LiveRanges::join()Matthias Braun2013-09-061-2/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190169 91177308-0d34-0410-b5e6-96231b3b80d8
| * fix typo in commentMatthias Braun2013-09-061-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190165 91177308-0d34-0410-b5e6-96231b3b80d8
| * mi-sched: Suppress register pressure tracking when the scheduling window is ↵Andrew Trick2013-09-041-2/+6
| | | | | | | | | | | | | | | | | | | | too small. If the instruction window is < NumRegs/2, pressure tracking is not likely to be effective. The scheduler has to process a very large number of tiny blocks. We want this to be fast. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189991 91177308-0d34-0410-b5e6-96231b3b80d8
| * mi-sched: bypass heuristic checks when regpressure tracking is disabled.Andrew Trick2013-09-041-0/+3
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189988 91177308-0d34-0410-b5e6-96231b3b80d8
| * Added -misched-regpressure option.Andrew Trick2013-09-042-2/+6
| | | | | | | | | | | | | | | | Register pressure tracking is half the complexity of the scheduler. It's useful to be able to turn it off for compile time and performance comparisons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189987 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix grammarMatt Arsenault2013-09-031-3/+3
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189855 91177308-0d34-0410-b5e6-96231b3b80d8
| * Free PressureDiffs instead of leaking.Benjamin Kramer2013-08-311-0/+1
| | | | | | | | | | | | Found by valgrind. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189725 91177308-0d34-0410-b5e6-96231b3b80d8
| * Use LiveRangeQuery for instruction-level liveness queries.Andrew Trick2013-08-301-15/+0
| | | | | | | | | | | | Remove redundant or bug-prone LiveInterval APIs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189685 91177308-0d34-0410-b5e6-96231b3b80d8
| * mi-sched: update PressureDiffs on-the-fly for liveness.Andrew Trick2013-08-303-2/+12
| | | | | | | | | | | | | | This removes all expensive pressure tracking logic from the scheduling critical path of node comparison. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189643 91177308-0d34-0410-b5e6-96231b3b80d8
| * Replace LiveInterval::killedAt with isKilledAtInstr.Andrew Trick2013-08-301-6/+7
| | | | | | | | | | | | Return true for LRGs that end at EarlyClobber or Register slots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189642 91177308-0d34-0410-b5e6-96231b3b80d8
| * mi-sched: improve the generic register pressure comparison.Andrew Trick2013-08-301-3/+2
| | | | | | | | | | | | | | Only compare pressure within the same set. When multiple sets are affected, we prioritize the most constrained set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189641 91177308-0d34-0410-b5e6-96231b3b80d8
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