aboutsummaryrefslogtreecommitdiffstats
path: root/include/llvm/Target/TargetInstrDesc.h
Commit message (Collapse)AuthorAgeFilesLines
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-291-4/+4
| | | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. WhenEvan Cheng2009-10-011-1/+23
| | | | | | | | | | | set, these flags indicate the instructions source / def operands have special register allocation requirement that are not captured in their register classes. Post-allocation passes (e.g. post-alloc scheduler) should not change their allocations. e.g. ARM::LDRD require the two definitions to be allocated even / odd register pair. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83196 91177308-0d34-0410-b5e6-96231b3b80d8
* 1. Introduce a new TargetOperandInfo::getRegClass() helper methodChris Lattner2009-07-291-3/+18
| | | | | | | | | | | | | | | and convert code to using it, instead of having lots of things poke the isLookupPtrRegClass() method directly. 2. Make PointerLikeRegClass contain a 'kind' int, and store it in the existing regclass field of TargetOperandInfo when the isLookupPtrRegClass() predicate is set. Make getRegClass pass this into TargetRegisterInfo::getPointerRegClass(), allowing targets to have multiple ptr_rc things. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77504 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new TargetInstrDesc::hasImplicitUseOfPhysReg andChris Lattner2009-04-121-0/+18
| | | | | | | | hasImplicitDefOfPhysReg methods. Use them to remove a look in X86 fast isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68886 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pr3954. The register scavenger asserts for inline assembly withBob Wilson2009-04-091-4/+0
| | | | | | | | | | | | | register destinations that are tied to source operands. The TargetInstrDescr::findTiedToSrcOperand method silently fails for inline assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very close to doing what is needed, so this revision makes a few changes to that method and also renames it to isRegTiedToUseOperand (for consistency with the very similar isRegTiedToDefOperand and because it handles both two-address instructions and inline assembly with tied registers). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68714 91177308-0d34-0410-b5e6-96231b3b80d8
* Clarify comments.Evan Cheng2009-02-051-3/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63851 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up #includes, deleting a bunch of unnecessary #includes.Dan Gohman2009-01-051-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
* Clarify a comment.Dan Gohman2008-12-221-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61338 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-031-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86'sDan Gohman2008-12-031-5/+8
| | | | | | | | | | | | | foldMemoryOperand how to "fold" them, by converting them into constant-pool loads. When they aren't folded, they use xorps/cmpeqd, but for example when register pressure is high, they may now be folded as memory operands, which reduces register pressure. Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will remat it instead of copying zeros around (V_SETALLONES was already marked). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60461 91177308-0d34-0410-b5e6-96231b3b80d8
* Add RCBarriers to TargetInstrDesc. It's a list of register classes the given ↵Evan Cheng2008-10-171-5/+19
| | | | | | | | | instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers. TableGen has been taught to generate the lists from instruction definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57722 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a flag to indicate that an instruction is as cheap (or cheaper) than a moveBill Wendling2008-05-281-1/+11
| | | | | | | | | | instruction to execute. This can be used for transformations (like two-address conversion) to remat an instruction instead of generating a "move" instruction. The idea is to decrease the live ranges and register pressure and all that jazz. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51660 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some minor errors in comments.Dan Gohman2008-04-091-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49445 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove isImplicitDef TargetInstrDesc flag.Evan Cheng2008-03-151-8/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48381 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove an invalid assertion now that there are implicit virtual register ↵Evan Cheng2008-02-221-2/+0
| | | | | | operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47493 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify the side effect stuff a bit more and make licm/sinkingChris Lattner2008-01-101-30/+13
| | | | | | | | | | | | | | | | | both work right according to the new flags. This removes the TII::isReallySideEffectFree predicate, and adds TII::isInvariantLoad. It removes NeverHasSideEffects+MayHaveSideEffects and adds UnmodeledSideEffects as machine instr flags. Now the clients can decide everything they need. I think isRematerializable can be implemented in terms of the flags we have now, though I will let others tackle that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45843 91177308-0d34-0410-b5e6-96231b3b80d8
* add a mayLoad property for machine instructions, a correlary to mayStore.Chris Lattner2008-01-081-2/+9
| | | | | | | This is currently not set by anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45748 91177308-0d34-0410-b5e6-96231b3b80d8
* split TargetInstrDesc out into its own header file.Chris Lattner2008-01-071-0/+414
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45696 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-03-06 21:04:36 +0000