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path: root/include/llvm/Target/TargetSelectionDAG.td
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* Add ARM patterns to match EXTRACT_SUBVECTOR nodes.Bob Wilson2011-01-071-0/+3
| | | | | | | | | | | | | | | Also fix an off-by-one in SelectionDAGBuilder that was preventing shuffle vectors from being translated to EXTRACT_SUBVECTOR. Patch by Tim Northover. The test changes are needed to keep those spill-q tests from testing aligned spills and restores. If the only aligned stack objects are spill slots, we no longer realign the stack frame. Prior to this patch, an EXTRACT_SUBVECTOR was legalized by loading from the stack, which created an aligned frame index. Now, however, there is nothing except the spill slot in the stack frame, so I added an aligned alloca. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122995 91177308-0d34-0410-b5e6-96231b3b80d8
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-231-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-231-15/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
* Prefetch has a MemOperand now. FileCheckize a test.Dale Johannesen2010-11-191-1/+2
| | | | | | | | This finishes up 8460971. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119848 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix preload instruction isel. Only v7 supports pli, and only v7 with mp ↵Evan Cheng2010-11-031-18/+18
| | | | | | extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
* Grammar.Jim Grosbach2010-10-151-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116557 91177308-0d34-0410-b5e6-96231b3b80d8
* add a common SDPatternOperator base class to SDNode and PatFrag forChris Lattner2010-10-071-2/+7
| | | | | | | | stuff that wants to take one or the other. These can both be used as the operation of a dag in a pattern match. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115877 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-211-0/+2
| | | | | | | | | | | | passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
* finally remove the immAllOnesV_bc/immAllZerosV_bc patternsChris Lattner2010-03-281-7/+0
| | | | | | | | | | | | and those derived from them. These are obnoxious because they were written as: PatLeaf<(bitconvert). Not having an argument was foiling adding better type checking for operand count matching up with what was required (in this case, bitconvert always requires an operand!) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99759 91177308-0d34-0410-b5e6-96231b3b80d8
* add some node definitions.Chris Lattner2010-03-281-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99745 91177308-0d34-0410-b5e6-96231b3b80d8
* remove parallel support.Chris Lattner2010-03-271-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99703 91177308-0d34-0410-b5e6-96231b3b80d8
* add a new SDNPVariadic SDNP node flag, and use it inChris Lattner2010-03-191-0/+1
| | | | | | | | | dag isel gen instead of instruction properties. This allows the oh-so-useful behavior of matching a variadic non-root node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98934 91177308-0d34-0410-b5e6-96231b3b80d8
* Make default expansion for FP16 <-> FP32 nodes into libcallsAnton Korobeynikov2010-03-141-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98501 91177308-0d34-0410-b5e6-96231b3b80d8
* remove a dead PatLeaf, I previously changed all uses to use -1 instead.Chris Lattner2010-02-251-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97148 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate some uses of immAllOnes, just use -1, it doesChris Lattner2010-02-211-1/+1
| | | | | | | | the same thing and is more efficient for the matcher. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96713 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the CPAttrParentAsRoot code, which is unused, and inconvenientDan Gohman2010-01-041-8/+1
| | | | | | | for a refactoring I'm working on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92503 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.Dan Gohman2009-11-231-7/+0
| | | | | | | | | Note that "hasDotLocAndDotFile"-style debug info was already broken; people wanting this functionality should implement it in the AsmPrinter/DwarfWriter code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a couple more target nodesNate Begeman2009-11-031-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85857 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial target-independent CodeGen support for BlockAddresses.Dan Gohman2009-10-301-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85556 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new "SDTCisVec" SDTypeConstraint. This complements the vAny type.Bob Wilson2009-08-121-2/+5
| | | | | | | | | There have been a few times where I've wanted this but ended up leaving the operand type unconstrained. It is easy to add this now and should help catch errors in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78849 91177308-0d34-0410-b5e6-96231b3b80d8
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-37/+37
| | | | | | | | | while the latter is capable of representing either a primitive or an extended type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-37/+37
| | | | | | own struct type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
* Major calling convention code refactoring.Dan Gohman2009-08-051-1/+0
| | | | | | | | | | | | | | | | | | | | Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
* Make IntInits and ListInits typed. This helps deduce types of !if andDavid Greene2009-06-081-0/+1
| | | | | | | | | other operators. For the rare cases where a list type cannot be deduced, provide a []<type> syntax, where <type> is the list element type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73078 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 72707 and 72709, for the moment.Dale Johannesen2009-06-021-6/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the implicit inputs and outputs of target-independentDale Johannesen2009-06-011-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust all target-independent code to use this format. Most targets will still produce a Flag-setting target-dependent version when selection is done. X86 is converted to use i32 instead, which means TableGen needs to produce different code in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit in xxxInstrInfo, currently set only for X86; in principle this is temporary and should go away when all other targets have been converted. All relevant X86 instruction patterns are modified to represent setting and using EFLAGS explicitly. The same can be done on other targets. The immediate behavior change is that an ADC/ADD pair are no longer tightly coupled in the X86 scheduler; they can be separated by instructions that don't clobber the flags (MOV). I will soon add some peephole optimizations based on using other instructions that set the flags to feed into ADC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
* 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.Nate Begeman2009-04-271-11/+2
| | | | | | | | | | | | | | | | PR2957 ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes as the shuffle mask. A value of -1 represents UNDEF. In addition to eliminating the creation of illegal BUILD_VECTORS just to represent shuffle masks, we are better about canonicalizing the shuffle mask, resulting in substantially better code for some classes of shuffles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70225 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 69952. Causes testsuite failures on linux x86-64.Rafael Espindola2009-04-241-2/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69967 91177308-0d34-0410-b5e6-96231b3b80d8
* PR2957Nate Begeman2009-04-241-11/+2
| | | | | | | | | | | | | | | ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes as the shuffle mask. A value of -1 represents UNDEF. In addition to eliminating the creation of illegal BUILD_VECTORS just to represent shuffle masks, we are better about canonicalizing the shuffle mask, resulting in substantially better code for some classes of shuffles. A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69952 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete ISD::INSERT_SUBREG and ISD::EXTRACT_SUBREG, which are unused.Dan Gohman2009-04-031-5/+0
| | | | | | | | Note that these are distinct from TargetInstrInfo::INSERT_SUBREG and TargetInstrInfo::EXTRACT_SUBREG, which are used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68355 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up the atomic opcodes in SelectionDAG.Dan Gohman2008-12-231-84/+64
| | | | | | | | | | | | | | This removes all the _8, _16, _32, and _64 opcodes and replaces each group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode is now used to carry the size information. In tablegen, the size-specific opcodes are replaced by size-independent opcodes that utilize the ability to compose them with predicates. This shrinks the per-opcode tables and makes the code that handles atomics much more concise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61389 91177308-0d34-0410-b5e6-96231b3b80d8
* Move target independent td files from lib/Target/ to include/llvm/Target so ↵Evan Cheng2008-11-241-0/+898
they can be distributed along with the header files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59953 91177308-0d34-0410-b5e6-96231b3b80d8
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