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* Remove noncopyableV base classes, as they were confusing the doxygen ↵Chris Lattner2003-06-034-10/+19
| | | | | | | | | documentation, making it harder to read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6575 91177308-0d34-0410-b5e6-96231b3b80d8
* Made a single common InvalidRegNum = -1.Vikram S. Adve2003-05-311-5/+8
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* Fixed misspelling and broke a line that was wrapping.Misha Brukman2003-05-291-2/+3
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* Allow allocation of a Sparc TargetMachine.Misha Brukman2003-05-271-2/+3
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* (1) Added special register class containing (for now) %fsr.Vikram S. Adve2003-05-271-10/+46
| | | | | | | | | | Fixed spilling of %fcc[0-3] which are part of %fsr. (2) Moved some machine-independent reg-class code to class TargetRegInfo from SparcReg{Class,}Info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6343 91177308-0d34-0410-b5e6-96231b3b80d8
* Make case of GetNumOfInt/FloatArgRegs functions to be use lower caseVikram S. Adve2003-05-251-2/+2
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* Reword to remove reference to how things worked in the past.Misha Brukman2003-05-241-4/+3
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* NOP instructions are pseudo-instructions. We should not have them explicitly inMisha Brukman2003-05-241-0/+14
| | | | | | | | | | | | our representation, since they are usually special cases of already-existing instructions. This abstracts away methods that let a pass create and verify a NOP instruction, without relying on a `NOP' enum to be in existence in the target's instruction info descriptor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6319 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove two fields from TargetData which are target specific.Chris Lattner2003-04-262-8/+1
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* Fix method name type-oChris Lattner2003-04-251-1/+1
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* Default ctor doesn't provide nameChris Lattner2003-04-251-1/+1
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* Add new targetdata ctor to create a targetdata appropriate to the moduleChris Lattner2003-04-241-1/+2
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* Must use std::pair instead of just 'pair'.Misha Brukman2003-04-071-1/+1
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* added a function and a member to the TargetSchedInfo classGuochun Shi2003-04-071-0/+18
| | | | | | | which is used by Modulo Scheduling pass git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5766 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify the interfaceChris Lattner2003-01-151-9/+1
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* Rename MachineInstrInfo -> TargetInstrInfoChris Lattner2003-01-144-401/+12
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* Move annotation to support libraryChris Lattner2003-01-141-1/+1
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* Rename MachineInstrInfo -> TargetInstrInfoChris Lattner2003-01-131-3/+3
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* * Start renaming MachineInstrInfo -> TargetInstrInfoChris Lattner2003-01-132-64/+86
| | | | | | | * Add new M_TERMINATOR_FLAG git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5213 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new getName methodChris Lattner2003-01-131-0/+7
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* More renamings of Target/Machine*Info to Target/Target*InfoChris Lattner2002-12-293-48/+33
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* Rename MachineOptInfo to TargetoptInfoChris Lattner2002-12-293-15/+14
| | | | | | | Rename MachineCacheInfo to TargetCacheInfo git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5203 91177308-0d34-0410-b5e6-96231b3b80d8
* * doxygenize commentChris Lattner2002-12-281-16/+10
| | | | | | | * rename MachineFrameInfo to TargetFrameInfo git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5170 91177308-0d34-0410-b5e6-96231b3b80d8
* Sparc specific methods default to abort rather than being pure virtualChris Lattner2002-12-282-42/+72
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* Expose some very simple information about the frame, rather than in-depthChris Lattner2002-12-281-46/+65
| | | | | | | target specific information. Rename MachineFrameInfo to TargetFrameInfo git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5168 91177308-0d34-0410-b5e6-96231b3b80d8
* * Keep track of register alignment as well as register sizeChris Lattner2002-12-281-35/+105
| | | | | | | | | | | | | | * Add comments * Add a new allocation_order iterator for register classes which targets may use to control the register order and available registers based on properties of the function being compiled. * Remove access to FP and SP registers * Add new callframe setup opcode support * Eliminate moveImm2Reg method * Revamp frame offset handling and prolog/epilog code generation git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5167 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify spill interface methodsChris Lattner2002-12-251-21/+21
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* Add commentChris Lattner2002-12-252-2/+2
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* Allow the target machines to specify endianness and pointer sizeChris Lattner2002-12-242-4/+20
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* Simplify interface to remove virtual function referencesChris Lattner2002-12-171-26/+50
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* Add support for register alias set descriptionChris Lattner2002-12-161-5/+16
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* Export well known instruction opcodes usable by target independant passesChris Lattner2002-12-152-0/+12
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* Simplify interfaces used by regalloc to insert codeChris Lattner2002-12-151-12/+9
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* Simplify TargetRegisterClass a bit, also eliminating virtual function callChris Lattner2002-12-151-14/+18
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* * Rename const_regclass_begin/end to just regclass_begin/endChris Lattner2002-12-151-23/+3
| | | | | | | | * Regclass iterators need an extra level of pointerness to work right * Pull inverse mapping code out of target description files git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5046 91177308-0d34-0410-b5e6-96231b3b80d8
* Added moveReg2Reg() and moveImm2Reg() to accomodate moving data around due toMisha Brukman2002-12-131-0/+10
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* Define the 2-address flag used by X86 instructions (add,sub,and,or,xor) thatMisha Brukman2002-12-122-2/+10
| | | | | | | need to be declared as such. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4975 91177308-0d34-0410-b5e6-96231b3b80d8
* Added prototypes for emitting prologue and epilogue for function codeMisha Brukman2002-12-041-0/+10
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* storeReg2RegOffset() and loadRegOffset2Reg() now take the iterator by valueMisha Brukman2002-12-041-2/+2
| | | | | | | instead of by reference, since they return the modified iterator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4914 91177308-0d34-0410-b5e6-96231b3b80d8
* Moved buildReg2RegClassMap() into from X86RegisterInfo to MRegisterInfo, sinceMisha Brukman2002-12-041-2/+8
| | | | | | | it is target-independent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4911 91177308-0d34-0410-b5e6-96231b3b80d8
* Expose target data through a method for uniformityChris Lattner2002-12-041-0/+1
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* RegisterInfo now supports handing out caller- and callee-save registers, asMisha Brukman2002-12-031-0/+17
| | | | | | | well as building a map from a physical register to its register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4896 91177308-0d34-0410-b5e6-96231b3b80d8
* Add entries to track information about implicit uses and definitions ofChris Lattner2002-12-032-4/+8
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* The hopefully final version of addPassesToEmitMachineCode which does notChris Lattner2002-12-021-3/+2
| | | | | | | have any question about ownership git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4863 91177308-0d34-0410-b5e6-96231b3b80d8
* Add comment about ownership semanticsChris Lattner2002-12-021-1/+2
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* Add stub to emit machine code for JITChris Lattner2002-12-021-7/+19
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* Added virtual functions for storing and retrieving values from the stack.Misha Brukman2002-11-221-9/+14
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* MRegisterInfo.h - Added prototypes for functions we need to map a register toMisha Brukman2002-11-202-6/+50
| | | | | | | | an appropriate TargetRegisterClass, also adds TargetRegisterClass definition. TargetMachine.h - speling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4781 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure that print gets a targetmachineChris Lattner2002-11-172-2/+4
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* Add machine independant printer interfaceChris Lattner2002-11-172-0/+12
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