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* Remove special-casing of return blocks for liveness.Jakob Stoklund Olesen2013-02-051-17/+1
| | | | | | | Now that return value registers are return instruction uses, there is no need for special treatment of return blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174416 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch addresses bug 15031.Bill Schmidt2013-01-281-8/+24
| | | | | | | | | | | | | | | | | | | | | | | The common code in the post-RA scheduler to break anti-dependencies on the critical path contained a flaw. In the reported case, an anti-dependency between the overlapping registers %X4 and %R4 exists: %X29<def> = OR8 %X4, %X4 %R4<def>, %X3<def,dead,tied3> = LBZU 1, %X3<kill,tied1> The unpatched code breaks the dependency by replacing %R4 and its uses with %R3, the first register on the available list. However, %R3 and %X3 overlap, so this creates two overlapping definitions on the same instruction. The fix is straightforward, preventing selection of a register that overlaps any other defined register on the same instruction. The test case is reduced from the bug report, and verifies that we no longer produce "lbzu 3, 1(3)" when breaking this anti-dependency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173706 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-3/+3
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
* Use MCPhysReg for RegisterClassInfo allocation orders.Jakob Stoklund Olesen2012-11-291-1/+1
| | | | | | This saves a bit of memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168852 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove RegisterClassInfo::isReserved() and isAllocatable().Jakob Stoklund Olesen2012-10-151-1/+1
| | | | | | Clients can use the equivalent functions in MRI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165990 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-021-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157885 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-15/+10
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch some getAliasSet clients to MCRegAliasIterator.Jakob Stoklund Olesen2012-06-011-34/+16
| | | | | | | MCRegAliasIterator can optionally visit the register itself, allowing for simpler code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157837 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-2/+2
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
* CriticalAntiDepBreaker: Replace a SmallSet of regs with a much denser BitVector.Benjamin Kramer2012-03-171-9/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152999 91177308-0d34-0410-b5e6-96231b3b80d8
* CriticalAntiDepBreaker: BasicBlock::size is an expensive operation, reuse ↵Benjamin Kramer2012-03-161-7/+7
| | | | | | | | the cached value. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152927 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-3/+3
| | | | | | static data size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-041-1/+1
| | | | | | size of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle regmasks in CriticalAntiDepBreaker.Jakob Stoklund Olesen2012-02-231-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151223 91177308-0d34-0410-b5e6-96231b3b80d8
* Initialize SUnits before DAG building.Andrew Trick2012-02-221-0/+2
| | | | | | | | | | | | Affect on SD scheduling and postRA scheduling: Printing the DAG will display the nodes in top-down topological order. This matches the order within the MBB and makes my life much easier in general. Affect on misched: We don't need to track virtual register uses at all. This is awesome. I also intend to rely on the SUnit ID as a topo-sort index. So if A < B then we cannot have an edge B -> A. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151135 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a late machine instruction copy propagation pass. This catchesEvan Cheng2012-01-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147716 91177308-0d34-0410-b5e6-96231b3b80d8
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-4/+4
| | | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-271-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach antidependency breakers to use RegisterClassInfo.Jakob Stoklund Olesen2011-06-161-8/+6
| | | | | | No functional change was intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133202 91177308-0d34-0410-b5e6-96231b3b80d8
* Update DBG_VALUEs while breaking anti dependencies.Devang Patel2011-06-021-9/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132487 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PostRA antidependence breaker.Andrew Trick2011-02-081-8/+46
| | | | | | | | | Avoid using the same register for two def operands or and earlyclobber def and use operand. This fixes PR8986 and improves on the prior fix for rdar://problem/8959122. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125089 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an anti-dep breaker corner case.Andrew Trick2011-02-051-1/+0
| | | | | | | | | | | | | | <rdar://problem/8959122> illegal register operands for UMULL instruction in cfrac nightly test I'm stil working on a unit test, but the case is: rx = movcc rx, r3 r2 = ldr r2, r3 = umull r2, r2 The anti-dep breaker should not convert this into an illegal instruction: r2, r2 = umull git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124932 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixes <rdar://problem/8612856>: During postRAsched, the antidependenceAndrew Trick2010-11-021-9/+27
| | | | | | | | breaker needs to check all definitions of the antidepenent register to avoid multiple defs of the same new register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118032 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a miscompile in 186.crafty for Thumb2 that was exposed by Evan'sBob Wilson2010-10-021-10/+14
| | | | | | | | | | | | scheduling change in svn 115121. The CriticalAntiDepBreaker had bad liveness information. It was calculating the KillIndices for one scheduling region in a basic block, rescheduling that region so the KillIndices were no longer valid, and then using those wrong KillIndices to make decisions for the next scheduling region. I've not been able to reduce a small testcase for this. Radar 8502534. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115400 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a comment typo.Bob Wilson2010-09-101-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113653 91177308-0d34-0410-b5e6-96231b3b80d8
* Anti-dependency breaking needs to be careful not to use reserved regsJim Grosbach2010-09-021-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112832 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a use-after-free.Dan Gohman2010-07-261-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109468 91177308-0d34-0410-b5e6-96231b3b80d8
* Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. This timeBill Wendling2010-07-151-9/+16
| | | | | | | make sure to allocate enough space in the std::vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108449 91177308-0d34-0410-b5e6-96231b3b80d8
* revert bill's patches in an attempt to fix the buildbot.Chris Lattner2010-07-151-4/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108419 91177308-0d34-0410-b5e6-96231b3b80d8
* Use std::vector instead of a hard-coded array. The length of that array couldBill Wendling2010-07-151-2/+4
| | | | | | | get *very* large, but we only need it to be the size of thenumber of pregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108411 91177308-0d34-0410-b5e6-96231b3b80d8
* Make post-ra scheduling, anti-dep breaking, and register scavenger ↵Evan Cheng2010-06-161-53/+84
| | | | | | (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
* Not all entries in the range will have an SUnit. Check for that when lookingJim Grosbach2010-06-021-0/+1
| | | | | | for debug information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105324 91177308-0d34-0410-b5e6-96231b3b80d8
* Update debug information when breaking anti-dependencies. rdar://7759363Jim Grosbach2010-06-011-1/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105300 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove trailing whitespaceJim Grosbach2010-05-141-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103807 91177308-0d34-0410-b5e6-96231b3b80d8
* Make BreakAntiDependencies' SUnits argument const, and make the BeginDan Gohman2010-04-191-13/+13
| | | | | | | and End arguments by-value rather than by-reference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101830 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some more places where dbg_value affected codegen.Dale Johannesen2010-03-051-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97765 91177308-0d34-0410-b5e6-96231b3b80d8
* Anti-dependency breaking needs to be careful regarding instructions withJim Grosbach2010-01-061-2/+7
| | | | | | multiple register definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92864 91177308-0d34-0410-b5e6-96231b3b80d8
* 80 column and whitespace cleanupJim Grosbach2010-01-061-5/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92837 91177308-0d34-0410-b5e6-96231b3b80d8
* Change errs() to dbgs().David Greene2010-01-041-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92490 91177308-0d34-0410-b5e6-96231b3b80d8
* <rdar://problem/7453528>. Track only physical registers that are valid for ↵David Goodwin2009-12-091-3/+6
| | | | | | the target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90970 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some old experimental code that is no longer needed. Remove ↵David Goodwin2009-11-201-1/+0
| | | | | | additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89471 91177308-0d34-0410-b5e6-96231b3b80d8
* Do a scheduling pass ignoring anti-dependencies to identify candidate ↵David Goodwin2009-11-031-1/+2
| | | | | | registers that should be renamed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85939 91177308-0d34-0410-b5e6-96231b3b80d8
* Break anti-dependence breaking out into its own class.David Goodwin2009-10-261-0/+539
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85127 91177308-0d34-0410-b5e6-96231b3b80d8
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