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* If known DebugLocs do not match then two DBG_VALUE machine instructions are ↵Devang Patel2011-07-071-0/+5
| | | | | | | | | | | | not identical. For example, DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ] DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ] These two MIs represent identical value, 3.31..., for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134620 91177308-0d34-0410-b5e6-96231b3b80d8
* Include a source location when complaining about bad inline assembly.Jakob Stoklund Olesen2011-07-021-0/+24
| | | | | | | | | | | | | | | | Add a MI->emitError() method that the backend can use to report errors related to inline assembly. Call it from X86FloatingPoint.cpp when the constraints are wrong. This enables proper clang diagnostics from the backend: $ clang -c pr30848.c pr30848.c:5:12: error: Inline asm output regs must be last on the x87 stack __asm__ ("" : "=u" (d)); /* { dg-error "output regs" } */ ^ 1 error generated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134307 91177308-0d34-0410-b5e6-96231b3b80d8
* Take a stab at fixing the llvm-x86_64-linux-checks failure.Cameron Zwarich2011-07-011-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134287 91177308-0d34-0410-b5e6-96231b3b80d8
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-55/+55
| | | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
* Distinguish early clobber output operands from clobbered registers.Jakob Stoklund Olesen2011-06-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we now use two different asm operand kinds. The new Kind_Clobber is treated identically to the old Kind_RegDefEarlyClobber for now, but x87 floating point stack inline assembly does care about the difference. This will pop a register off the stack: asm("fstp %st" : : "t"(x) : "st"); While this will pop the input and push an output: asm("fst %st" : "=&t"(r) : "t"(x)); We need to know if ST0 was a clobber or an output operand, and we can't depend on <dead> flags for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133902 91177308-0d34-0410-b5e6-96231b3b80d8
* Decode and pretty print inline asm operand descriptors.Jakob Stoklund Olesen2011-06-271-1/+22
| | | | | | | | | | The INLINEASM MachineInstrs have an immediate operand describing each original inline asm operand. Decode the bits in MachineInstr::print() so it is easier to read: INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133901 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle debug info for i128 constants.Devang Patel2011-06-241-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133821 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-commit 131172 with fix. MachineInstr identity checks should check deadEvan Cheng2011-05-121-7/+23
| | | | | | | | | | markers. In some cases a register def is dead on one path, but not on another. This is passing Clang self-hosting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131214 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove an assertion to fix PR9872.Jakob Stoklund Olesen2011-05-081-1/+2
| | | | | | | | | | | | | | | | | | | | It can happen that a live debug variable is the last use of a sub-register, and the register allocator will pick a larger register class for the virtual register. If the allocated register doesn't support the sub-register index, just use %noreg for the debug variables instead of asserting. In PR9872, a debug variable ends up in the sub_8bit_hi part of a GR32_ABCD register. The register is split and one part is inflated to GR32 and assigned %ESI because there are no more normal uses of sub_8bit_hi. Since %ESI doesn't have that sub-register, substPhysReg asserted. Now it will simply insert a %noreg instead, and the debug variable will be marked unavailable in that range. We don't currently have a way of saying: !"value" is in bits 8-15 of %ESI, I don't know if DWARF even supports that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131073 91177308-0d34-0410-b5e6-96231b3b80d8
* Print out the 'nontemporal' info on a store.Bill Wendling2011-04-291-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130562 91177308-0d34-0410-b5e6-96231b3b80d8
* Ensure all defs referring to a virtual register are marked dead by ↵Jakob Stoklund Olesen2011-04-051-7/+2
| | | | | | | | | | | | addRegisterDead(). There can be multiple defs for a single virtual register when they are defining sub-registers. The missing <dead> flag was stopping the inline spiller from eliminating dead code after rematerialization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128888 91177308-0d34-0410-b5e6-96231b3b80d8
* Add FrameSetup MI flagsAnton Korobeynikov2011-03-051-10/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127098 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-101-6/+4
| | | | | | | | These functions not longer assert when passed 0, but simply return false instead. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace TargetRegisterInfo::printReg with a PrintReg class that also works ↵Jakob Stoklund Olesen2011-01-091-17/+4
| | | | | | | | | | without a TRI instance. Print virtual registers numbered from 0 instead of the arbitrary FirstVirtualRegister. The first virtual register is printed as %vreg0. TRI::NoRegister is printed as %noreg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123107 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-8/+49
| | | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
* DBG_VALUE does not have any side effects; it also makes no sense to mark it ↵Evan Cheng2011-01-071-1/+3
| | | | | | cheap as a copy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123031 91177308-0d34-0410-b5e6-96231b3b80d8
* Unbreak build.Evan Cheng2010-10-221-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117155 91177308-0d34-0410-b5e6-96231b3b80d8
* Make CodeGen TBAA-aware.Dan Gohman2010-10-201-3/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116890 91177308-0d34-0410-b5e6-96231b3b80d8
* Shrink MachineOperand from 40 to 32 bytes on 64-bit hosts.Jakob Stoklund Olesen2010-10-191-3/+3
| | | | | | | | | | | | | Pull an unsigned out of the Contents union such that it has the same size as two pointers and no padding. Arrange members such that the Contents union and all pointers can be 8-byte aligned without padding. This speeds up code generation by 0.8% on a 64-bit host. 32-bit hosts should be unaffected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116857 91177308-0d34-0410-b5e6-96231b3b80d8
* convert a couple more places to use the new getStore()Chris Lattner2010-09-211-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114463 91177308-0d34-0410-b5e6-96231b3b80d8
* add some accessorsChris Lattner2010-09-211-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114409 91177308-0d34-0410-b5e6-96231b3b80d8
* it's more elegant to put the "getConstantPool" andChris Lattner2010-09-211-0/+12
| | | | | | | | | "getFixedStack" on the MachinePointerInfo class. While this isn't the problem I'm setting out to solve, it is the right way to eliminate PseudoSourceValue, so lets go with it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114406 91177308-0d34-0410-b5e6-96231b3b80d8
* add some helpful accessors.Chris Lattner2010-09-211-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114400 91177308-0d34-0410-b5e6-96231b3b80d8
* start pushing MachinePointerInfo out through the MachineMemOperand interfaceChris Lattner2010-09-211-4/+5
| | | | | | | to the MachineFunction construction methods. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114390 91177308-0d34-0410-b5e6-96231b3b80d8
* refactor the Value*/offset pair from MachineMemOperand out to a newChris Lattner2010-09-211-5/+5
| | | | | | | | | | MachinePointerInfo struct, no functionality change. This also adds an assert to MachineMemOperand::MachineMemOperand that verifies that the Value* is either null or is an IR pointer type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114389 91177308-0d34-0410-b5e6-96231b3b80d8
* Prefix `next' iterator operation with `llvm::'.Oscar Fuentes2010-08-021-1/+1
| | | | | | | | | Fixes potential ambiguity problems on VS 2010. Patch by nobled! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110029 91177308-0d34-0410-b5e6-96231b3b80d8
* Print out the regclass of any virtual registers used by a machine instruction.Jakob Stoklund Olesen2010-07-281-0/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109608 91177308-0d34-0410-b5e6-96231b3b80d8
* Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG.Jakob Stoklund Olesen2010-07-041-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107602 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate the AlignStack bit in InlineAsm's to the Dale Johannesen2010-07-021-7/+7
| | | | | | | | | | | | | | | | | | | | | PrologEpilog code, and use it to determine whether the asm forces stack alignment or not. gcc consistently does not do this for GCC-style asms; Apple gcc inconsistently sometimes does it for asm blocks. There is no convenient place to put a bit in either the SDNode or the MachineInstr form, so I've added an extra operand to each; unlovely, but it does allow for expansion for more bits, should we need it. PR 5125. Some existing testcases are affected. The operand lists of the SDNode and MachineInstr forms are indexed with awesome mnemonics, like "2"; I may fix this someday, but not now. I'm not making it any worse. If anyone is inspired I think you can find all the right places from this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107506 91177308-0d34-0410-b5e6-96231b3b80d8
* Print InlinedAt location.Devang Patel2010-06-291-12/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107208 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach regular and fast isel to set dead flags on unused implicit defsDan Gohman2010-06-181-0/+19
| | | | | | | on calls and similar instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106353 91177308-0d34-0410-b5e6-96231b3b80d8
* Slightly change the meaning of the reMaterialize target hook when the originalJakob Stoklund Olesen2010-06-021-0/+23
| | | | | | | | | | | | | | | | | | | | | | | instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly compose subregister indices when coalescing.Jakob Stoklund Olesen2010-06-011-1/+2
| | | | | | | The comment about ordering of subreg indices is no longer true. This exposed a bug in the new substVirtReg method that is also fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105294 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a TargetRegisterInfo::composeSubRegIndices hook with a defaultJakob Stoklund Olesen2010-05-281-0/+19
| | | | | | | | | | implementation that is correct for most targets. Tablegen will override where needed. Add MachineOperand::subst{Virt,Phys}Reg methods that correctly handle existing subreg indices when sustituting registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104985 91177308-0d34-0410-b5e6-96231b3b80d8
* Print symbolic SubRegIndex names on machine operands.Jakob Stoklund Olesen2010-05-251-2/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
* - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defsEvan Cheng2010-05-211-9/+14
| | | | | | | | | | | that are aliases of the specified register. - Rename modifiesRegister to definesRegister since it's looking a def of the specific register or one of its super-registers. It's not looking for def of a sub-register or alias that could change the specified register. - Added modifiesRegister to look for defs of aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104377 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MachineInstr::readsWritesVirtualRegister() to determine if an instructionJakob Stoklund Olesen2010-05-211-11/+15
| | | | | | | | | | reads or writes a register. This takes partial redefines and undef uses into account. Don't actually use it yet. That caused miscompiles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104372 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a ↵Jakob Stoklund Olesen2010-05-211-15/+11
| | | | | | | | register is read." This reverts r104322. I think it was causing miscompilations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104323 91177308-0d34-0410-b5e6-96231b3b80d8
* Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.Jakob Stoklund Olesen2010-05-211-11/+15
| | | | | | This correctly handles partial redefines and undef uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104322 91177308-0d34-0410-b5e6-96231b3b80d8
* If the first definition of a virtual register is a partial redef, add anJakob Stoklund Olesen2010-05-211-5/+15
| | | | | | | <imp-def> operand for the full register. This ensures that the full physical register is marked live after register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104320 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MachineInstr::readsVirtualRegister() in preparation for proper handling ofJakob Stoklund Olesen2010-05-191-1/+24
| | | | | | | | | | | | | | | | | | partial redefines. We are going to treat a partial redefine of a virtual register as a read-modify-write: %reg1024:6 = OP Unless the register is fully clobbered: %reg1024:6 = OP, %reg1024<imp-def> MachineInstr::readsVirtualRegister() knows the difference. The first case is a read, the second isn't. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104149 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach MachineLICM and MachineSink how to clear kill flags conservativelyDan Gohman2010-05-131-0/+10
| | | | | | | when they move instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103737 91177308-0d34-0410-b5e6-96231b3b80d8
* Pretty print DBG_VALUE machine instructions.Evan Cheng2010-04-281-1/+9
| | | | | | | | | | Before: DBG_VALUE %RSI, 0, !-1; dbg:SimpleRegisterCoalescing.cpp:2707 Now: DBG_VALUE %RSI, 0, !"this"; dbg:SimpleRegisterCoalescing.cpp:2707 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102518 91177308-0d34-0410-b5e6-96231b3b80d8
* Use getNumImplicitDefs() and getNumImplicitUses().Bob Wilson2010-04-091-24/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100850 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix up some comments.Bob Wilson2010-04-091-5/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100849 91177308-0d34-0410-b5e6-96231b3b80d8
* Coalescer should not delete copy instructions whose defs are partially dead. ↵Evan Cheng2010-04-081-0/+13
| | | | | | | | | e.g. %RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100804 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a latent bug my inline asm stuff exposed: Chris Lattner2010-04-071-0/+2
| | | | | | | MachineOperand::isIdenticalTo wasn't handling metadata operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100636 91177308-0d34-0410-b5e6-96231b3b80d8
* stop using DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-5/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100215 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch the code generator (except the JIT) onto the new DebugLocChris Lattner2010-04-021-5/+4
| | | | | | | | | | | | | | | | | representation. This eliminates the 'DILocation' MDNodes for file/line/col tuples from -O0 -g codegen. This remove the old DebugLoc class, making it a typedef for DebugLoc, I'll rename NewDebugLoc next. I didn't update the JIT to use the new apis, so it will continue to work, but be as slow as before. Someone should eventually do this or, better yet, rip out the JIT debug info stuff and build the JIT on top of MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100209 91177308-0d34-0410-b5e6-96231b3b80d8
* add support for MCSymbols as operands to MachineInstrs.Chris Lattner2010-03-131-25/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98433 91177308-0d34-0410-b5e6-96231b3b80d8
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