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* Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper2012-03-081-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152301 91177308-0d34-0410-b5e6-96231b3b80d8
* Try to clarify this comment some.Chandler Carruth2012-03-071-4/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152221 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove another outbreak of customized (and completely broken) hashing.Chandler Carruth2012-03-071-20/+24
| | | | | | | | | | | | | | | This one is particularly annoying because the hashing algorithm is highly specialized, with a strange "equivalence" definition that subsets the fields involved. Still, this looks at the exact same set of data as the old code, but without bitwise or-ing over parts of it and other mixing badness. No functionality changed here. I've left a substantial fixme about the fact that there is a cleaner and more principled way to do this, but it requires making the equality definition actual stable for particular types... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152218 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
* Move getBundleStart() into MachineInstrBundle.h.Jakob Stoklund Olesen2012-03-011-10/+0
| | | | | | | | | This allows the function to be inlined, and makes it suitable for use in getInstructionIndex(). Also provide a const version. C++ is great for touch typing practice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151782 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverse iterator - should be incrementing rather than decrementing.Lang Hames2012-02-171-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150778 91177308-0d34-0410-b5e6-96231b3b80d8
* Make LiveIntervals::handleMove() bundle aware.Lang Hames2012-02-151-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150630 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle regmasks in findRegisterDefOperandIdx().Jakob Stoklund Olesen2012-02-141-0/+4
| | | | | | | | | | | Only accept register masks when looking for an 'overlapping' def. When Overlap is not set, the function searches for a proper definition of Reg. This means MI->modifiesRegister() considers register masks, but MI->definesRegister() doesn't. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150529 91177308-0d34-0410-b5e6-96231b3b80d8
* Put instruction names into an indexed string table on the side, removing a ↵Benjamin Kramer2012-02-101-1/+4
| | | | | | | | | pointer from MCInstrDesc. Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150245 91177308-0d34-0410-b5e6-96231b3b80d8
* Added MachineInstr::isBundled() to check if an instruction is part of a bundle.Andrew Trick2012-02-081-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150044 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle register mask operands in setPhysRegsDeadExcept().Jakob Stoklund Olesen2012-02-031-0/+12
| | | | | | | | | | | Calls that use register mask operands don't have implicit defs for returned values. The register mask operand handles the call clobber, but it always behaves like a set of dead defs. Add live implicit defs for any implicitly defined physregs that are actually used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149715 91177308-0d34-0410-b5e6-96231b3b80d8
* ArrayRef'ize MI::setPhysRegsDeadExcept().Jakob Stoklund Olesen2012-02-031-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149709 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle all live physreg defs in the same place.Jakob Stoklund Olesen2012-02-031-1/+1
| | | | | | | | | | | SelectionDAG has 4 different ways of passing physreg defs to users. Collect all of the uses at the same time, and pass all of them to MI->setPhysRegsDeadExcept() to mark the remaining defs dead. The setPhysRegsDeadExcept() function will soon add the required implicit-defs to instructions with register mask operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149708 91177308-0d34-0410-b5e6-96231b3b80d8
* Require non-NULL register masks.Jakob Stoklund Olesen2012-02-021-1/+1
| | | | | | | It doesn't seem worthwhile to give meaning to a NULL register mask pointer. It complicates all the code using register mask operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149646 91177308-0d34-0410-b5e6-96231b3b80d8
* Clear kill flags before propagating a copy.Jakob Stoklund Olesen2012-01-261-0/+14
| | | | | | | | | | The live range of the source register may be extended when a redundant copy is eliminated. Make sure any kill flags between the two copies are cleared. This fixes PR11765. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149069 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new kind of MachineOperand: MO_RegisterMask.Jakob Stoklund Olesen2012-01-161-0/+5
| | | | | | | | | | | | | | | | | | | | | Register masks will be used as a compact representation of large clobber lists. Currently, an x86 call instruction has some 40 operands representing call-clobbered registers. That's more than 1kB of useless operands per call site. A register mask operand references a bit mask of call-preserved registers, everything else is clobbered. The bit mask will typically come from TargetRegisterInfo::getCallPreservedMask(). By abandoning ImplicitDefs for call-clobbered registers, it also becomes possible to share call instruction descriptions between calling conventions, and we can get rid of the WINCALL* instructions. This patch introduces the new operand kind. Future patches will add RegMask support to target-independent passes before finally the fixed clobber lists can be removed from call instruction descriptions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148250 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 'llvm_unreachable' to passify GCC's understanding of the constraintsChandler Carruth2012-01-101-0/+1
| | | | | | | | of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147861 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-101-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147855 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-141-13/+38
| | | | | | | | | | | to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542 91177308-0d34-0410-b5e6-96231b3b80d8
* Make MachineInstr instruction property queries more flexible. This change allEvan Cheng2011-12-081-5/+5
| | | | | | | | | clients to decide whether to look inside bundled instructions and whether the query should return true if any / all bundled instructions have the queried property. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146168 91177308-0d34-0410-b5e6-96231b3b80d8
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-14/+27
| | | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing check.Jakob Stoklund Olesen2011-12-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146004 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MachineOperand IsInternalRead flag.Jakob Stoklund Olesen2011-12-071-5/+18
| | | | | | | This flag is used when bundling machine instructions. It indicates whether the operand reads a value defined inside or outside its bundle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145997 91177308-0d34-0410-b5e6-96231b3b80d8
* First chunk of MachineInstr bundle support.Evan Cheng2011-12-061-0/+35
| | | | | | | | | | 1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
* Added invariant field to the DAG.getLoad method and changed all calls.Pete Cooper2011-11-081-0/+1
| | | | | | | When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144100 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverted r143600 - selector reference changePete Cooper2011-11-031-15/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143646 91177308-0d34-0410-b5e6-96231b3b80d8
* Treat objc selector reference globals as invariant so that MachineLICM can ↵Pete Cooper2011-11-031-0/+15
| | | | | | hoist them out of loops. Fixes <rdar://problem/6027699> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143600 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing braces to pacify GCC's -Wparentheses.Nick Lewycky2011-10-131-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141842 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MachineInstr::getRegClassConstraint().Jakob Stoklund Olesen2011-10-121-0/+33
| | | | | | | | | Most instructions have some requirements for their register operands. Usually, this is expressed as register class constraints in the MCInstrDesc, but for inline assembly the constraints are encoded in the flag words. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141835 91177308-0d34-0410-b5e6-96231b3b80d8
* Extract a method for finding the inline asm flag operand.Jakob Stoklund Olesen2011-10-121-30/+38
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141834 91177308-0d34-0410-b5e6-96231b3b80d8
* Encode register class constreaints in inline asm instructions.Jakob Stoklund Olesen2011-10-121-8/+17
| | | | | | | | | | | | | The inline asm operand constraint is initially encoded in the virtual register for the operand, but that register class may change during coalescing, and the original constraint is lost. Encode the original register class as part of the flag word for each inline asm operand. This makes it possible to recover the actual constraint required by inline asm, just like we can for normal instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141833 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove NumImplicitOps which is now unused.Jakob Stoklund Olesen2011-09-291-18/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140767 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite MachineInstr::addOperand() to avoid NumImplicitOps.Jakob Stoklund Olesen2011-09-291-81/+53
| | | | | | | | | | | | | | | | | | | | | | | The function needs to scan the implicit operands anyway, so no performance is won by caching the number of implicit operands added to an instruction. This also fixes a bug when adding operands after an implicit operand has been added manually. The NumImplicitOps count wasn't kept up to date. MachineInstr::addOperand() will now consistently place all explicit operands before all the implicit operands, regardless of the order they are added. It is possible to change an MI opcode and add additional explicit operands. They will be inserted before any existing implicit operands. The only exception is inline asm instructions where operands are never reordered. This is because of a hack that marks explicit clobber regs on inline asm as <implicit-def> to please the fast register allocator. This hack can go away when InstrEmitter and FastIsel can add exact <dead> flags to physreg defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140744 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 parsing and encoding for IT blocks.Jim Grosbach2011-08-291-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138773 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Trailing whitespace.Jim Grosbach2011-08-241-31/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138437 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't treat a partial <def,undef> operand as a read.Jakob Stoklund Olesen2011-08-191-1/+2
| | | | | | | | | | | | | | | | | | | | | | | Normally, a partial register def is treated as reading the super-register unless it also defines the full register like this: %vreg110:sub_32bit<def> = COPY %vreg77:sub_32bit, %vreg110<imp-def> This patch also uses the <undef> flag on partial defs to recognize non-reading operands: %vreg110:sub_32bit<def,undef> = COPY %vreg77:sub_32bit This fixes a subtle bug in RegisterCoalescer where LIS->shrinkToUses would treat a coalesced copy as still reading the register, extending the live range artificially. My test case only works when I disable DCE so a dead copy is left for RegisterCoalescer, so I am not including it. <rdar://problem/9967101> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138018 91177308-0d34-0410-b5e6-96231b3b80d8
* Print DBG_VALUE variable's location info as a comment.Devang Patel2011-08-041-1/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136916 91177308-0d34-0410-b5e6-96231b3b80d8
* If known DebugLocs do not match then two DBG_VALUE machine instructions are ↵Devang Patel2011-07-071-0/+5
| | | | | | | | | | | | not identical. For example, DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ] DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ] These two MIs represent identical value, 3.31..., for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134620 91177308-0d34-0410-b5e6-96231b3b80d8
* Include a source location when complaining about bad inline assembly.Jakob Stoklund Olesen2011-07-021-0/+24
| | | | | | | | | | | | | | | | Add a MI->emitError() method that the backend can use to report errors related to inline assembly. Call it from X86FloatingPoint.cpp when the constraints are wrong. This enables proper clang diagnostics from the backend: $ clang -c pr30848.c pr30848.c:5:12: error: Inline asm output regs must be last on the x87 stack __asm__ ("" : "=u" (d)); /* { dg-error "output regs" } */ ^ 1 error generated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134307 91177308-0d34-0410-b5e6-96231b3b80d8
* Take a stab at fixing the llvm-x86_64-linux-checks failure.Cameron Zwarich2011-07-011-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134287 91177308-0d34-0410-b5e6-96231b3b80d8
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-55/+55
| | | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
* Distinguish early clobber output operands from clobbered registers.Jakob Stoklund Olesen2011-06-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we now use two different asm operand kinds. The new Kind_Clobber is treated identically to the old Kind_RegDefEarlyClobber for now, but x87 floating point stack inline assembly does care about the difference. This will pop a register off the stack: asm("fstp %st" : : "t"(x) : "st"); While this will pop the input and push an output: asm("fst %st" : "=&t"(r) : "t"(x)); We need to know if ST0 was a clobber or an output operand, and we can't depend on <dead> flags for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133902 91177308-0d34-0410-b5e6-96231b3b80d8
* Decode and pretty print inline asm operand descriptors.Jakob Stoklund Olesen2011-06-271-1/+22
| | | | | | | | | | The INLINEASM MachineInstrs have an immediate operand describing each original inline asm operand. Decode the bits in MachineInstr::print() so it is easier to read: INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133901 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle debug info for i128 constants.Devang Patel2011-06-241-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133821 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-commit 131172 with fix. MachineInstr identity checks should check deadEvan Cheng2011-05-121-7/+23
| | | | | | | | | | markers. In some cases a register def is dead on one path, but not on another. This is passing Clang self-hosting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131214 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove an assertion to fix PR9872.Jakob Stoklund Olesen2011-05-081-1/+2
| | | | | | | | | | | | | | | | | | | | It can happen that a live debug variable is the last use of a sub-register, and the register allocator will pick a larger register class for the virtual register. If the allocated register doesn't support the sub-register index, just use %noreg for the debug variables instead of asserting. In PR9872, a debug variable ends up in the sub_8bit_hi part of a GR32_ABCD register. The register is split and one part is inflated to GR32 and assigned %ESI because there are no more normal uses of sub_8bit_hi. Since %ESI doesn't have that sub-register, substPhysReg asserted. Now it will simply insert a %noreg instead, and the debug variable will be marked unavailable in that range. We don't currently have a way of saying: !"value" is in bits 8-15 of %ESI, I don't know if DWARF even supports that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131073 91177308-0d34-0410-b5e6-96231b3b80d8
* Print out the 'nontemporal' info on a store.Bill Wendling2011-04-291-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130562 91177308-0d34-0410-b5e6-96231b3b80d8
* Ensure all defs referring to a virtual register are marked dead by ↵Jakob Stoklund Olesen2011-04-051-7/+2
| | | | | | | | | | | | addRegisterDead(). There can be multiple defs for a single virtual register when they are defining sub-registers. The missing <dead> flag was stopping the inline spiller from eliminating dead code after rematerialization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128888 91177308-0d34-0410-b5e6-96231b3b80d8
* Add FrameSetup MI flagsAnton Korobeynikov2011-03-051-10/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127098 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-101-6/+4
| | | | | | | | These functions not longer assert when passed 0, but simply return false instead. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
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