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path: root/lib/CodeGen/MachineScheduler.cpp
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* misched: Add finalizeScheduler to complete the target interface.Andrew Trick2012-04-011-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153827 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: trace LiveIntervals after scheduling.Andrew Trick2012-03-211-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153161 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: obvious iterator update fixes for bottom-up.Andrew Trick2012-03-211-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153160 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: cleanup main loopAndrew Trick2012-03-211-10/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153159 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an option to the MI scheduler to cut off scheduling after a fixed number ofLang Hames2012-03-191-1/+19
| | | | | | | | instructions have been scheduled. Handy for tracking down scheduler bugs, or bugs exposed by scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153045 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence operator precedence warnings.Benjamin Kramer2012-03-141-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152711 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: implemented a framework for top-down or bottom-up scheduling.Andrew Trick2012-03-141-98/+266
| | | | | | | | | | | | | | | | | | | New flags: -misched-topdown, -misched-bottomup. They can be used with the default scheduler or with -misched=shuffle. Without either topdown/bottomup flag -misched=shuffle now alternates scheduling direction. LiveIntervals update is unimplemented with bottom-up scheduling, so only -misched-topdown currently works. Capped the ScheduleDAG hierarchy with a concrete ScheduleDAGMI class. ScheduleDAGMI is aware of the top and bottom of the unscheduled zone within the current region. Scheduling policy can be plugged into the ScheduleDAGMI driver by implementing MachineSchedStrategy. ConvergingScheduler is now the default scheduling algorithm. It exercises the new driver but still does no reordering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152700 91177308-0d34-0410-b5e6-96231b3b80d8
* misched commentsAndrew Trick2012-03-141-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152699 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: handle scheduler that insert instructions at empty region boundaries.Andrew Trick2012-03-091-3/+12
| | | | | | And add comments, since this is obviously confusing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152445 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: handle scheduling region boundaries nicely.Andrew Trick2012-03-091-4/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152393 91177308-0d34-0410-b5e6-96231b3b80d8
* misched interface: rename Begin/End to RegionBegin/RegionEnd since they are ↵Andrew Trick2012-03-091-3/+3
| | | | | | not private. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152382 91177308-0d34-0410-b5e6-96231b3b80d8
* misched commentsAndrew Trick2012-03-091-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152374 91177308-0d34-0410-b5e6-96231b3b80d8
* revert 152356: verify misched changes using -misched=shuffle.Andrew Trick2012-03-091-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152373 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: allow the default scheduler to be one chosen by the target.Andrew Trick2012-03-091-16/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152360 91177308-0d34-0410-b5e6-96231b3b80d8
* Cache MBB->begin. It's possible the scheduler / bundler may change MBB->begin().Evan Cheng2012-03-091-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152356 91177308-0d34-0410-b5e6-96231b3b80d8
* misched interface: Expose the MachineScheduler pass.Andrew Trick2012-03-081-144/+102
| | | | | | | | Allow targets to provide their own schedulers (subclass of ScheduleDAGInstrs) to the misched pass. Select schedulers using -misched=... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152278 91177308-0d34-0410-b5e6-96231b3b80d8
* misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick2012-03-071-1/+1
| | | | | | implement their own MachineScheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152261 91177308-0d34-0410-b5e6-96231b3b80d8
* misched prep: rename InsertPos to End.Andrew Trick2012-03-071-1/+1
| | | | | | ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152256 91177308-0d34-0410-b5e6-96231b3b80d8
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-071-12/+12
| | | | | | | We had half the API with one convention, half with another. Now was a good time to clean it up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152255 91177308-0d34-0410-b5e6-96231b3b80d8
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-071-10/+16
| | | | | | | | | | | | | | | | | | | ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152208 91177308-0d34-0410-b5e6-96231b3b80d8
* Added -view-misched=dags options.Andrew Trick2012-03-071-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152178 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Use the StartBlock/FinishBlock hooksAndrew Trick2012-03-071-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152172 91177308-0d34-0410-b5e6-96231b3b80d8
* Initialize SUnits before DAG building.Andrew Trick2012-02-221-6/+7
| | | | | | | | | | | | Affect on SD scheduling and postRA scheduling: Printing the DAG will display the nodes in top-down topological order. This matches the order within the MBB and makes my life much easier in general. Affect on misched: We don't need to track virtual register uses at all. This is awesome. I also intend to rely on the SUnit ID as a topo-sort index. So if A < B then we cannot have an edge B -> A. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151135 91177308-0d34-0410-b5e6-96231b3b80d8
* MachineScheduler shouldn't use/preserve LiveDebugVariables.Lang Hames2012-02-171-4/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150773 91177308-0d34-0410-b5e6-96231b3b80d8
* Disentangle moving a machine instr from updating LiveIntervals.Lang Hames2012-02-151-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150552 91177308-0d34-0410-b5e6-96231b3b80d8
* RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick2012-02-101-8/+0
| | | | | | | | | | | | | | | | Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
* commentAndrew Trick2012-02-091-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150121 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: bug in debug output.Andrew Trick2012-02-081-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150043 91177308-0d34-0410-b5e6-96231b3b80d8
* stale commentAndrew Trick2012-02-081-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150041 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a "moveInstr" method to LiveIntervals. This can be used to move instructionsLang Hames2012-01-271-1/+3
| | | | | | | | | | around within a basic block while maintaining live-intervals. Updated ScheduleTopDownLive in MachineScheduler.cpp to use the moveInstr API when reordering MIs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149147 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Inital interface and implementation for ScheduleTopDownLive and ↵Andrew Trick2012-01-171-17/+130
| | | | | | ShuffleInstructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148291 91177308-0d34-0410-b5e6-96231b3b80d8
* Renamed MachineScheduler to ScheduleTopDownLive.Andrew Trick2012-01-171-47/+59
| | | | | | Responding to code review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148290 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Initial code for building an MI level scheduling DAGAndrew Trick2012-01-141-10/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148174 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Added ScheduleDAGInstrs::IsPostRAAndrew Trick2012-01-141-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148172 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Invoke the DAG builder on each sequence of schedulable instructions.Andrew Trick2012-01-141-6/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148171 91177308-0d34-0410-b5e6-96231b3b80d8
* Move things around to make the file navigable, even though it will probably ↵Andrew Trick2012-01-141-19/+32
| | | | | | be split up later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148170 91177308-0d34-0410-b5e6-96231b3b80d8
* Added the MachineSchedulerPass skeleton.Andrew Trick2012-01-131-0/+233
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148105 91177308-0d34-0410-b5e6-96231b3b80d8
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