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* Fix a typo (the the => the)Sylvestre Ledru2012-07-231-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: allow NULL InstrItineraries.Andrew Trick2012-07-021-0/+1
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* misched: avoid scheduling instructions that can't be dispatched.Andrew Trick2012-06-291-6/+29
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* misched: count micro-ops toward the issue limit.Andrew Trick2012-06-291-10/+19
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* Guard private fields that are unused in Release builds with #ifndef NDEBUG.Benjamin Kramer2012-06-161-1/+7
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* Move RegisterClassInfo.h.Andrew Trick2012-06-061-1/+1
| | | | | | | Allow targets to access this API. It's required for RegisterPressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158102 91177308-0d34-0410-b5e6-96231b3b80d8
* Move RegisterPressure.h.Andrew Trick2012-06-061-1/+1
| | | | | | | Make it a general utility for use by Targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158097 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-051-31/+81
| | | | | | | Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: comments from code review.Andrew Trick2012-06-051-3/+3
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* misched: trace formattingAndrew Trick2012-05-251-6/+5
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* Silence unused variable warnings from when assertions are disabled.Kaelyn Uhrain2012-05-241-0/+2
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* misched: Use the same scheduling heuristics with -misched-topdown/bottomup.Andrew Trick2012-05-241-2/+16
| | | | | | (except the part about choosing direction) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157437 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Trace regpressure.Andrew Trick2012-05-241-2/+4
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* misched: Give each ReadyQ a unique IDAndrew Trick2012-05-241-36/+45
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* misched: Added ScoreboardHazardRecognizer.Andrew Trick2012-05-241-49/+232
| | | | | | | | | | | | | | | | | | | The Hazard checker implements in-order contraints, or interlocked resources. Ready instructions with hazards do not enter the available queue and are not visible to other heuristics. The major code change is the addition of SchedBoundary to encapsulate the state at the top or bottom of the schedule, including both a pending and available queue. The scheduler now counts cycles in sync with the hazard checker. These are minimum cycle counts based on known hazards. Targets with no itinerary (x86_64) currently remain at cycle 0. To fix this, we need to provide some maximum issue width for all targets. We also need to add the concept of expected latency vs. minimum latency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157427 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Release bottom roots in reverse order.Andrew Trick2012-05-241-9/+23
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* misched: rename ReadyQ classAndrew Trick2012-05-241-8/+9
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* misched: copy comments so compareRPDelta is readable by itself.Andrew Trick2012-05-241-1/+4
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* commentsAndrew Trick2012-05-171-2/+3
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* misched: trace ReadyQ.Andrew Trick2012-05-171-0/+8
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* misched: Added 3-level regpressure back-off.Andrew Trick2012-05-171-36/+184
| | | | | | | | | | | | | | | | | | | Introduce the basic strategy for register pressure scheduling. 1) Respect target limits at all times. 2) Indentify critical register classes (pressure sets). Track pressure within the scheduled region. Avoid increasing scheduled pressure for critical registers. 3) Avoid exceeding the max pressure of the region prior to scheduling. Added logic for picking between the top and bottom ready Q's based on regpressure heuristics. Status: functional but needs to be asjusted to achieve good results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157006 91177308-0d34-0410-b5e6-96231b3b80d8
* commentAndrew Trick2012-05-171-2/+0
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* misched: fix liveness iteratorsAndrew Trick2012-05-171-10/+16
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* misched: Print machineinstrs with -debug-only=mischedAndrew Trick2012-05-101-0/+2
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* misched: tracing register pressure heuristics.Andrew Trick2012-05-101-6/+22
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* misched: Add register pressure backoff to ConvergingScheduler.Andrew Trick2012-05-101-38/+144
| | | | | | | | | | | | Prioritize the instruction that comes closest to keeping pressure under the target's limit. Then prioritize instructions that avoid increasing the max pressure in the scheduled region. The max pressure heuristic is a tad aggressive. Later I'll fix it to consider the unscheduled pressure as well. WIP: This is mostly functional but untested and not likely to do much good yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156574 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Release only unscheduled nodes into ReadyQ.Andrew Trick2012-05-101-2/+8
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* misched: Added ReadyQ container wrapper for Top and Bottom Queues.Andrew Trick2012-05-101-11/+44
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* misched: Introducing Top and Bottom register pressure trackers during ↵Andrew Trick2012-05-101-10/+71
| | | | | | scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156571 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a naughty header include that breaks "installed" builds.Andrew Trick2012-04-241-2/+12
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* misched: try (not too hard) to place debug values where they belongAndrew Trick2012-04-241-0/+25
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* misched: ignore debug values during schedulingAndrew Trick2012-04-241-6/+31
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* misched: DAG builder support for tracking register pressure within the ↵Andrew Trick2012-04-241-4/+48
| | | | | | | | | current scheduling region. The DAG builder is a convenient place to do it. Hopefully this is more efficient than a separate traversal over the same region. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155456 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Add finalizeScheduler to complete the target interface.Andrew Trick2012-04-011-0/+1
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* misched: trace LiveIntervals after scheduling.Andrew Trick2012-03-211-0/+1
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* misched: obvious iterator update fixes for bottom-up.Andrew Trick2012-03-211-0/+6
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* misched: cleanup main loopAndrew Trick2012-03-211-10/+14
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* Add an option to the MI scheduler to cut off scheduling after a fixed number ofLang Hames2012-03-191-1/+19
| | | | | | | | instructions have been scheduled. Handy for tracking down scheduler bugs, or bugs exposed by scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153045 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence operator precedence warnings.Benjamin Kramer2012-03-141-3/+3
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* misched: implemented a framework for top-down or bottom-up scheduling.Andrew Trick2012-03-141-98/+266
| | | | | | | | | | | | | | | | | | | New flags: -misched-topdown, -misched-bottomup. They can be used with the default scheduler or with -misched=shuffle. Without either topdown/bottomup flag -misched=shuffle now alternates scheduling direction. LiveIntervals update is unimplemented with bottom-up scheduling, so only -misched-topdown currently works. Capped the ScheduleDAG hierarchy with a concrete ScheduleDAGMI class. ScheduleDAGMI is aware of the top and bottom of the unscheduled zone within the current region. Scheduling policy can be plugged into the ScheduleDAGMI driver by implementing MachineSchedStrategy. ConvergingScheduler is now the default scheduling algorithm. It exercises the new driver but still does no reordering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152700 91177308-0d34-0410-b5e6-96231b3b80d8
* misched commentsAndrew Trick2012-03-141-0/+15
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* misched: handle scheduler that insert instructions at empty region boundaries.Andrew Trick2012-03-091-3/+12
| | | | | | And add comments, since this is obviously confusing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152445 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: handle scheduling region boundaries nicely.Andrew Trick2012-03-091-4/+11
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* misched interface: rename Begin/End to RegionBegin/RegionEnd since they are ↵Andrew Trick2012-03-091-3/+3
| | | | | | not private. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152382 91177308-0d34-0410-b5e6-96231b3b80d8
* misched commentsAndrew Trick2012-03-091-2/+3
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* revert 152356: verify misched changes using -misched=shuffle.Andrew Trick2012-03-091-3/+3
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* misched: allow the default scheduler to be one chosen by the target.Andrew Trick2012-03-091-16/+33
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* Cache MBB->begin. It's possible the scheduler / bundler may change MBB->begin().Evan Cheng2012-03-091-3/+3
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* misched interface: Expose the MachineScheduler pass.Andrew Trick2012-03-081-144/+102
| | | | | | | | Allow targets to provide their own schedulers (subclass of ScheduleDAGInstrs) to the misched pass. Select schedulers using -misched=... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152278 91177308-0d34-0410-b5e6-96231b3b80d8
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