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* When scheduling a block in parts, keep track of the overallDan Gohman2009-02-111-3/+16
| | | | | | | | | | | | instruction index across each part. Instruction indices are used to make live range queries, and live ranges can extend beyond scheduling region boundaries. Refactor the ScheduleDAGSDNodes class some more so that it doesn't have to worry about this additional information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64288 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor out more code for computing register live-range informationforDan Gohman2009-02-101-120/+40
| | | | | | | | | | | | scheduling, and generalize is so that preserves state across scheduling regions. This fixes incorrect live-range information around terminators and labels, which are effective region boundaries. In place of looking for terminators to anchor inter-block dependencies, introduce special entry and exit scheduling units for this purpose. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64254 91177308-0d34-0410-b5e6-96231b3b80d8
* Move ScheduleDAGInstrs.h to be a private header. Front-endsDan Gohman2009-02-061-1/+1
| | | | | | | | | that used this header to select a scheduling policy should use SchedulerRegistry.h instead (llvm-gcc and clang were updated a while ago). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63934 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a post-RA scheduling dependency bug.Dan Gohman2009-01-301-11/+90
| | | | | | | | | | | | | | | | If a MachineInstr doesn't have a memoperand but has an opcode that is known to load or store, assume its memory reference may alias *anything*, including stack slots which the compiler completely controls. To partially compensate for this, teach the ScheduleDAG building code to do basic getUnderlyingValue analysis. This greatly reduces the number of instructions that require restrictive dependencies. This code will need to be revisited when we start doing real alias analysis, but it should suffice for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63370 91177308-0d34-0410-b5e6-96231b3b80d8
* Instead of adding dependence edges between terminator instructionsDan Gohman2009-01-161-10/+34
| | | | | | | | | | | | | | | and every other instruction in their blocks to keep the terminator instructions at the end, teach the post-RA scheduler how to operate on ranges of instructions, and exclude terminators from the range of instructions that get scheduled. Also, exclude mid-block labels, such as EH_LABEL instructions, and schedule code before them separately from code after them. This fixes problems with the post-RA scheduler moving code past EH_LABELs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62366 91177308-0d34-0410-b5e6-96231b3b80d8
* Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman2009-01-151-18/+21
| | | | | | | | | | | | and into the ScheduleDAGInstrs class, so that they don't get destructed and re-constructed for each block. This fixes a compile-time hot spot in the post-pass scheduler. To help facilitate this, tidy and do some minor reorganization in the scheduler constructor functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up the atomic opcodes in SelectionDAG.Dan Gohman2008-12-231-0/+1
| | | | | | | | | | | | | | This removes all the _8, _16, _32, and _64 opcodes and replaces each group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode is now used to carry the size information. In tablegen, the size-specific opcodes are replaced by size-independent opcodes that utilize the ability to compose them with predicates. This shrinks the per-opcode tables and makes the code that handles atomics much more concise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61389 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename BuildSchedUnits to BuildSchedGraph, and refactor theDan Gohman2008-12-231-1/+1
| | | | | | | code in ScheduleDAGSDNodes' BuildSchedGraph into separate functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61376 91177308-0d34-0410-b5e6-96231b3b80d8
* Use isTerminator() instead of isBranch()||isReturn() inDan Gohman2008-12-231-3/+2
| | | | | | | | | several places. isTerminator() returns true for a superset of cases, and includes things like FP_REG_KILL, which are nither return or branch but aren't safe to move/remat/etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61373 91177308-0d34-0410-b5e6-96231b3b80d8
* Add initial support for back-scheduling address computations,Dan Gohman2008-12-161-1/+132
| | | | | | | | especially in the case of addresses computed from loop induction variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61075 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some register-alias-related bugs in the post-RA scheduler livenessDan Gohman2008-12-161-18/+50
| | | | | | | | | | | | | | | computation code. Also, avoid adding output-depenency edges when both defs are dead, which frequently happens with EFLAGS defs. Compute Depth and Height lazily, and always in terms of edge latency values. For the schedulers that don't care about latency, edge latencies are set to 1. Eliminate Cycle and CycleBound, and LatencyPriorityQueue's Latencies array. These are all subsumed by the Depth and Height fields. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61073 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a simple target-independent heuristic to allow targets with noDan Gohman2008-12-161-0/+6
| | | | | | | instruction itinerary data to back-schedule loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61070 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite the SDep class, and simplify some of the related code.Dan Gohman2008-12-091-23/+24
| | | | | | | | | | | | | | | | | | The Cost field is removed. It was only being used in a very limited way, to indicate when the scheduler should attempt to protect a live register, and it isn't really needed to do that. If we ever want the scheduler to start inserting copies in non-prohibitive situations, we'll have to rethink some things anyway. A Latency field is added. Instead of giving each node a single fixed latency, each edge can have its own latency. This will eventually be used to model various micro-architecture properties more accurately. The PointerIntPair class and an internal union are now used, which reduce the overall size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60806 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the top-level comments, and fix some 80-column violations.Dan Gohman2008-12-081-7/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60707 91177308-0d34-0410-b5e6-96231b3b80d8
* Add minimal support for disambiguating memory references. CurrentlyDan Gohman2008-12-041-13/+123
| | | | | | | the main thing this covers is spills to distinct spill slots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60517 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass the isAntiDep argument.Dan Gohman2008-11-241-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59968 91177308-0d34-0410-b5e6-96231b3b80d8
* Correctly set the isCtrl flag for chain dependencies.Dan Gohman2008-11-211-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59837 91177308-0d34-0410-b5e6-96231b3b80d8
* Update comments.Dan Gohman2008-11-211-9/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59836 91177308-0d34-0410-b5e6-96231b3b80d8
* Set the isAntiDep flag in the MachineInstr scheduler.Dan Gohman2008-11-211-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59787 91177308-0d34-0410-b5e6-96231b3b80d8
* Use ComputeLatency in the MachineInstr scheduler.Dan Gohman2008-11-211-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59777 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement ComputeLatency for MachineInstr ScheduleDAGs. FactorDan Gohman2008-11-211-1/+10
| | | | | | | | | some of the latency computation logic out of the SDNode ScheduleDAG code into a TargetInstrItineraries helper method to help with this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59761 91177308-0d34-0410-b5e6-96231b3b80d8
* Treat mid-block labels the same as terminators when building theDan Gohman2008-11-201-1/+1
| | | | | | | | | | | MachineInstr scheduling DAG, meaning they implicitly depend on all preceding defs. This fixes Benchmarks/Shootout-C++/except and Regression/C++/EH/simple_rethrow in -relocation-model=pic -disable-post-RA-scheduler=false mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59747 91177308-0d34-0410-b5e6-96231b3b80d8
* Experimental post-pass scheduling support. Post-pass schedulingDan Gohman2008-11-191-0/+135
is currently off by default, and can be enabled with -disable-post-RA-scheduler=false. This doesn't have a significant impact on most code yet because it doesn't yet do anything to address anti-dependencies and it doesn't attempt to disambiguate memory references. Also, several popular targets don't have pipeline descriptions yet. The majority of the changes here are splitting the SelectionDAG-specific code out of ScheduleDAG, so that ScheduleDAG can be moved to libLLVMCodeGen.a. The interface between ScheduleDAG-using code and the rest of the scheduling code is somewhat rough and will evolve. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59676 91177308-0d34-0410-b5e6-96231b3b80d8
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