aboutsummaryrefslogtreecommitdiffstats
path: root/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Don't narrow the load and store in a load+twiddle+store sequence unlessDan Gohman2010-09-021-1/+2
| | | | | | | | | | | there are clearly no stores between the load and the store. This fixes this miscompile reported as PR7833. This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is safe, but awkward to prove safe. Move it to X86's README.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112861 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a crash in the dag combiner caused by ↵Nate Begeman2010-07-271-2/+10
| | | | | | | | | ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself recursively and returning a SCALAR_TO_VECTOR node, but assuming the input was always a BUILD_VECTOR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109519 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove r108639 now that it is handled by InstCombine instead.Owen Anderson2010-07-191-13/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108688 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a DAGCombine xform to fold away redundant float->double->float ↵Owen Anderson2010-07-181-0/+13
| | | | | | | | | | | conversions around sqrt instructions. I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this. This fixed <rdar://problem/8197504>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108639 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert some tab stops into spaces.Duncan Sands2010-07-121-28/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108130 91177308-0d34-0410-b5e6-96231b3b80d8
* Reenable DAG combining for vector shuffles. It looks like it was temporarilyBob Wilson2010-07-091-2/+0
| | | | | | | | | disabled and then never turned back on again. Adjust some tests, one because this change avoids an unnecessary instruction, and the other to make it continue testing what it was intended to test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge the duplicated iabs optimization in DAGCombiner and let it detected a ↵Benjamin Kramer2010-07-081-30/+26
| | | | | | few more idioms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107868 91177308-0d34-0410-b5e6-96231b3b80d8
* Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument ↵Evan Cheng2010-07-071-22/+23
| | | | | | for consistency sake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107820 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate debug loc.Devang Patel2010-07-061-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8
* Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so theyBob Wilson2010-06-281-1/+2
| | | | | | | | can't be changed arbitrarily by the DAGCombiner without checking if it is running after legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107097 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove variables which are assigned to but for which the valueDuncan Sands2010-06-251-1/+0
| | | | | | | is not used. Spotted by gcc-4.6. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106854 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r106634, now that the bug it exposed is fixed.Dan Gohman2010-06-241-8/+37
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106746 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r106263, "Fold the ShrinkDemandedOps pass into the regular ↵Daniel Dunbar2010-06-231-37/+8
| | | | | | DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106634 91177308-0d34-0410-b5e6-96231b3b80d8
* Some targets don't require the fencing MEMBARRIER instructions surroundingJim Grosbach2010-06-231-0/+55
| | | | | | | | atomic intrinsics, either because the use locking instructions for the atomics, or because they perform the locking directly. Add support in the DAG combiner to fold away the fences. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106630 91177308-0d34-0410-b5e6-96231b3b80d8
* Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,Dan Gohman2010-06-181-8/+37
| | | | | | | which is faster, simpler, and less surprising. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106263 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix another variant of PR 7191. Also add a testcaseDale Johannesen2010-05-251-1/+5
| | | | | | | | | | Mon Ping provided; unfortunately bugpoint failed to reduce it, but I think it's important to have a test for this in the suite. 8023512. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104624 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR 7191. I have been unable to create a .ll file that fails, sorry.Dale Johannesen2010-05-251-2/+10
| | | | | | | | | (oye, a word which should be better known to people writing tree traversals, means grandchild.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104619 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up extra whitespace.Bob Wilson2010-05-211-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104410 91177308-0d34-0410-b5e6-96231b3b80d8
* Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elementsBob Wilson2010-05-211-0/+7
| | | | | | | | | so that it will continue to test what it was meant to test when I commit a separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon. Fix a DAG combiner crash exposed by this test change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104380 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize away insertelement of an undef value. This shows up inBob Wilson2010-05-191-0/+4
| | | | | | | | test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code because the coalescer cleans it up. Radar 7998853. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104185 91177308-0d34-0410-b5e6-96231b3b80d8
* Intrinsics which do a vector compare (results are all zero or all ones) are ↵Evan Cheng2010-05-191-6/+75
| | | | | | | | | | | modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction. The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that. Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104094 91177308-0d34-0410-b5e6-96231b3b80d8
* Sink dag combine's post index load / store code that swap base ptr and index ↵Evan Cheng2010-05-181-4/+0
| | | | | | into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060 91177308-0d34-0410-b5e6-96231b3b80d8
* FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op ↵Evan Cheng2010-05-181-7/+8
| | | | | | (build_vector), (build_vector)). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104004 91177308-0d34-0410-b5e6-96231b3b80d8
* Be careful with operand promotion. For a binary operation, the source ↵Evan Cheng2010-05-101-4/+10
| | | | | | operands may be the same. PR7018. rdar://7939869. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103419 91177308-0d34-0410-b5e6-96231b3b80d8
* Apply a patch from Jan Sjodin to fix a compiler abort on vectorDan Gohman2010-04-301-9/+24
| | | | | | | | comparisons sign-extended to a different bitwidth than the comparison operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102721 91177308-0d34-0410-b5e6-96231b3b80d8
* Try operation promotion only if regular dag combine and target-specific ones ↵Evan Cheng2010-04-281-15/+42
| | | | | | failed to do anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102492 91177308-0d34-0410-b5e6-96231b3b80d8
* - When legal, promote a load to zextload rather than ext load.Evan Cheng2010-04-271-6/+20
| | | | | | | - Catch more further dag combine opportunities as result of operand promotion, e.g. (i32 anyext (i16 trunc (i32 x))) -> (i32 x) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102455 91177308-0d34-0410-b5e6-96231b3b80d8
* When a load operand is promoted to an extload, replace other uses with uses ↵Evan Cheng2010-04-241-30/+67
| | | | | | of extload result truncated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102236 91177308-0d34-0410-b5e6-96231b3b80d8
* Apply a fix for a vector setcc dagcombine from Jan Sjodin. NoDan Gohman2010-04-241-1/+2
| | | | | | | testcase yet, as the testcase now fails downstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102228 91177308-0d34-0410-b5e6-96231b3b80d8
* Code refactoring.Evan Cheng2010-04-231-11/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102202 91177308-0d34-0410-b5e6-96231b3b80d8
* - It's not safe to promote rotates (at least not trivially).Evan Cheng2010-04-221-25/+46
| | | | | | | - Some code refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102111 91177308-0d34-0410-b5e6-96231b3b80d8
* The visitXOR method can return the same SDNode. If so, we don't want to deleteBill Wendling2010-04-201-1/+1
| | | | | | | it as it's not dead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101855 91177308-0d34-0410-b5e6-96231b3b80d8
* More progress on promoting i16 operations to i32 for x86. Work in progress.Evan Cheng2010-04-191-9/+118
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101808 91177308-0d34-0410-b5e6-96231b3b80d8
* More work to allow dag combiner to promote 16-bit ops to 32-bit.Evan Cheng2010-04-171-24/+96
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101621 91177308-0d34-0410-b5e6-96231b3b80d8
* (i32 sext_in_reg (i32 aext (i16 x)), i16) -> (i32 sext x). No known test ↵Evan Cheng2010-04-161-1/+2
| | | | | | case until -promote-16bit is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101551 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding support for dag combiner to promote operations for profit. This ↵Evan Cheng2010-04-161-6/+47
| | | | | | | | | | | requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding. x86 support is off by default. It can be enabled with -promote-16bit. Work in progress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101448 91177308-0d34-0410-b5e6-96231b3b80d8
* enhance the load/store narrowing optimization to handle aChris Lattner2010-04-151-5/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tokenfactor in between the load/store. This allows us to optimize test7 into: _test7: ## @test7 ## BB#0: ## %entry movl (%rdx), %eax ## kill: SIL<def> ESI<kill> movb %sil, 5(%rdi) ret instead of: _test7: ## @test7 ## BB#0: ## %entry movl 4(%esp), %ecx movl $-65281, %eax ## imm = 0xFFFFFFFFFFFF00FF andl 4(%ecx), %eax movzbl 8(%esp), %edx shll $8, %edx addl %eax, %edx movl 12(%esp), %eax movl (%eax), %eax movl %edx, 4(%ecx) ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101355 91177308-0d34-0410-b5e6-96231b3b80d8
* teach codegen to turn trunc(zextload) into load when possible.Chris Lattner2010-04-151-1/+1
| | | | | | | | | This doesn't occur much at all, it only seems to formed in the case when the trunc optimization kicks in due to phase ordering. In that case it is saves a few bytes on x86-32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101350 91177308-0d34-0410-b5e6-96231b3b80d8
* add a simple dag combine to replace trivial shl+lshr withChris Lattner2010-04-151-0/+9
| | | | | | | and. This happens with the store->load narrowing stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101348 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement rdar://7860110 (also in target/readme.txt) narrowingChris Lattner2010-04-151-22/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a load/or/and/store sequence into a narrower store when it is safe. Daniel tells me that clang will start producing this sort of thing with bitfields, and this does trigger a few dozen times on 176.gcc produced by llvm-gcc even now. This compiles code like CodeGen/X86/2009-05-28-DAGCombineCrash.ll into: movl %eax, 36(%rdi) instead of: movl $4294967295, %eax ## imm = 0xFFFFFFFF andq 32(%rdi), %rax shlq $32, %rcx addq %rax, %rcx movq %rcx, 32(%rdi) and each of the testcases into a single store. Each of them used to compile into craziness like this: _test4: movl $65535, %eax ## imm = 0xFFFF andl (%rdi), %eax shll $16, %esi addl %eax, %esi movl %esi, (%rdi) ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101343 91177308-0d34-0410-b5e6-96231b3b80d8
* Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman2010-04-151-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary parens.Dan Gohman2010-04-121-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101010 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix -Wsign-compare warning (issued by clang++).Ted Kremenek2010-04-081-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100799 91177308-0d34-0410-b5e6-96231b3b80d8
* fix 80 col violation, patch by Alastair LynnChris Lattner2010-04-071-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100639 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix sdisel memcpy, memset, memmove lowering:Evan Cheng2010-04-011-23/+23
| | | | | | | | | | | | | | 1. Makes it possible to lower with floating point loads and stores. 2. Avoid unaligned loads / stores unless it's fast. 3. Fix some memcpy lowering logic bug related to when to optimize a load from constant string into a constant. 4. Adjust x86 memcpy lowering threshold to make it more sane. 5. Fix x86 target hook so it uses vector and floating point memory ops more effectively. rdar://7774704 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100090 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR6533 by updating the br(xor) code to remember the caseChris Lattner2010-03-101-5/+7
| | | | | | | when it looked past a trunc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98203 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix another bitwidth calculation to handle vector types; based on aDan Gohman2010-03-101-1/+1
| | | | | | | patch by Micah Villmow for PR6572. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98188 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix more code to work properly with vector operands. Based onDan Gohman2010-03-041-5/+5
| | | | | | | a patch my Micah Villmow for PR6465. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97692 91177308-0d34-0410-b5e6-96231b3b80d8
* Use APInt instead of zext value.Bill Wendling2010-03-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97631 91177308-0d34-0410-b5e6-96231b3b80d8
* This test case:Bill Wendling2010-03-031-5/+7
| | | | | | | | | | | | | | | | | | | | | | long test(long x) { return (x & 123124) | 3; } Currently compiles to: _test: orl $3, %edi movq %rdi, %rax andq $123127, %rax ret This is because instruction and DAG combiners canonicalize (or (and x, C), D) -> (and (or, D), (C | D)) However, this is only profitable if (C & D) != 0. It gets in the way of the 3-addressification because the input bits are known to be zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97616 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-06-03 17:36:12 +0000