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* - Change MachineInstr::isIdenticalTo to take a new option that determines ↵Evan Cheng2010-03-031-31/+5
| | | | | | | | | whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality. - Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97628 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Target hook to duplicate machine instructions.Jakob Stoklund Olesen2010-01-061-0/+7
| | | | | | | Some instructions refer to unique labels, and so cannot be trivially cloned with CloneMachineInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92873 91177308-0d34-0410-b5e6-96231b3b80d8
* improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner2009-12-031-1/+1
| | | | | | | Patch by Howard Hinnant! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90365 91177308-0d34-0410-b5e6-96231b3b80d8
* Check if subreg index is zero.Evan Cheng2009-11-161-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88899 91177308-0d34-0410-b5e6-96231b3b80d8
* - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.Evan Cheng2009-11-141-3/+8
| | | | | | | | | - If destination is a physical register and it has a subreg index, use the sub-register instead. This fixes PR5423. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88745 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdenticalEvan Cheng2009-11-071-0/+31
| | | | | | | | | | | except it doesn't care if the definitions' virtual registers differ. This is used by machine LICM and other MI passes to perform CSE. - Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical. Since pc relative constantpool entries are always different, this requires it it check if the values can actually the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86328 91177308-0d34-0410-b5e6-96231b3b80d8
* -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixedEvan Cheng2009-10-181-4/+1
| | | | | | | | | | | | stack slots and giving them different PseudoSourceValue's did not fix the problem of post-alloc scheduling miscompiling llvm itself. - Apply Dan's conservative workaround by assuming any non fixed stack slots can alias other memory locations. This means a load from spill slot #1 cannot move above a store of spill slot #2. - Enable post-alloc scheduling for x86 at optimization leverl Default and above. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
* Only fixed stack objects and spill slots should be get FixedStack ↵Evan Cheng2009-10-181-1/+4
| | | | | | PseudoSourceValue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84411 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 84315 for now. Re-thinking the patch.Evan Cheng2009-10-171-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84321 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename getFixedStack to getStackObject. The stack objects represented are notEvan Cheng2009-10-171-1/+1
| | | | | | | necessarily fixed. Only those will negative frame indices are "fixed." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84315 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert the kludge in 76703. I got a cleanDale Johannesen2009-10-121-21/+0
| | | | | | | | | | | bootstrap of FSF-style PPC, so there is some reason to believe the original bug (which was never analyzed) has been fixed, probably by 82266. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83871 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor out LiveIntervalAnalysis' code to determine whether an instructionDan Gohman2009-10-091-0/+88
| | | | | | | | | | | | | | | is trivially rematerializable and integrate it into TargetInstrInfo::isTriviallyReMaterializable. This way, all places that need to know whether an instruction is rematerializable will get the same answer. This enables the useful parts of the aggressive-remat option by default -- using AliasAnalysis to determine whether a memory location is invariant, and removes the questionable parts -- rematting operations with virtual register inputs that may not be live everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83687 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve MachineMemOperand handling.Dan Gohman2009-09-251-8/+8
| | | | | | | | | | | | | | | | | | | | | | - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
* Change MachineMemOperand's alignment value to be the alignment ofDan Gohman2009-09-211-1/+1
| | | | | | | | the base pointer, without the offset. This matches MemSDNode's new alignment behavior, and holds more interesting information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82473 91177308-0d34-0410-b5e6-96231b3b80d8
* Let each target determines whether a machine instruction is dead. If true, ↵Evan Cheng2009-07-221-0/+21
| | | | | | | | | that allows late codeine passes to delete it. This is considered a workaround. The problem is some targets are not modeling side effects correctly. PPC is apparently one of those. This patch allows ppc llvm-gcc to bootstrap on Darwin. Once we find out which instruction definitions are wrong, we can remove the PPCInstrInfo workaround. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76703 91177308-0d34-0410-b5e6-96231b3b80d8
* Let callers decide the sub-register index on the def operand of ↵Evan Cheng2009-07-161-1/+4
| | | | | | | | | rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
* Use findCommutedOpIndices to find the operands to commute.Evan Cheng2009-07-101-3/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75312 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove TargetInstrInfo::CommuteChangesDestination and added ↵Evan Cheng2009-07-101-18/+16
| | | | | | findCommutedOpIndices which returns the operand indices which are swapped (when applicable). This allows for some code clean up and future enhancements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75264 91177308-0d34-0410-b5e6-96231b3b80d8
* CommuteChangesDestination() should check if to-be-commuted instruction ↵Evan Cheng2009-07-011-16/+30
| | | | | | defines any register. Also teaches the default commuteInstruction() to commute instruction without definitions (e.g. X86::test / ARM::tsp). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74602 91177308-0d34-0410-b5e6-96231b3b80d8
* Change MachineInstrBuilder::addReg() to take a flag instead of a list ofBill Wendling2009-05-131-3/+3
| | | | | | | | | | | | | booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
* Explicitly pass in debug location information to BuildMI.Bill Wendling2009-02-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63599 91177308-0d34-0410-b5e6-96231b3b80d8
* Split foldMemoryOperand into public non-virtual and protected virtualDan Gohman2008-12-031-0/+68
| | | | | | | | parts, and add target-independent code to add/preserve MachineMemOperands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60488 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-5/+5
| | | | | | | isReg, etc., from isRegister, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove isImm(), isReg(), and friends, in favor of Dan Gohman2008-09-131-3/+3
| | | | | | | | | | isImmediate(), isRegister(), and friends, to avoid confusion about having two different names with the same meaning. I'm not attached to the longer names, and would be ok with changing to the shorter names if others prefer it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56189 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a 80 column violation.Evan Cheng2008-09-111-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56097 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert uses of std::vector in TargetInstrInfo to SmallVector. This change ↵Owen Anderson2008-08-141-1/+2
| | | | | | had to be propoagated down into all the targets and up into all clients of this API. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54802 91177308-0d34-0410-b5e6-96231b3b80d8
* Pool-allocation for MachineInstrs, MachineBasicBlocks, andDan Gohman2008-07-071-2/+4
| | | | | | | | | | | | MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
* Add option to commuteInstruction() which forces it to create a new ↵Evan Cheng2008-06-161-2/+17
| | | | | | (commuted) instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52308 91177308-0d34-0410-b5e6-96231b3b80d8
* Infrastructure for getting the machine code size of a function and an ↵Nicolas Geoffray2008-04-161-0/+11
| | | | | | instruction. X86, PowerPC and ARM are implemented git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49809 91177308-0d34-0410-b5e6-96231b3b80d8
* Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.Evan Cheng2008-03-311-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48995 91177308-0d34-0410-b5e6-96231b3b80d8
* Added CommuteChangesDestination(). This returns true if commuting the specifiedEvan Cheng2008-02-151-1/+21
| | | | | | | machine instr will change its definition register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47166 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify.Evan Cheng2008-02-131-3/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47058 91177308-0d34-0410-b5e6-96231b3b80d8
* commuteInstr() can now commute non-ssa machine instrs.Evan Cheng2008-02-131-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47043 91177308-0d34-0410-b5e6-96231b3b80d8
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-16/+17
| | | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
* Add predicates methods to TargetOperandInfo, and switch all clients Chris Lattner2008-01-071-1/+1
| | | | | | | | over to using them, instead of diddling Flags directly. Change the various flags from const variables to enums. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45677 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflectsChris Lattner2008-01-071-2/+2
| | | | | | | | | | | | | | | | | | that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a problem where lib/Target/TargetInstrInfo.h would include and useChris Lattner2008-01-011-0/+58
a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8
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