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* More removal of std::cerr and DEBUG, replacing with DOUT instead.Bill Wendling2006-11-171-38/+44
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31806 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed some spiller bugs exposed by the recent two-address code changes. NowEvan Cheng2006-11-041-21/+53
| | | | | | | | | | there may be other def(s) apart from the use&def two-address operand. We need to check if the register reuse for a use&def operand may conflicts with another def. Provide a mean to recover from the conflict if it is detected when the defs are processed later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31439 91177308-0d34-0410-b5e6-96231b3b80d8
* RenameEvan Cheng2006-11-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31364 91177308-0d34-0410-b5e6-96231b3b80d8
* Two-address instructions no longer have to be A := A op C. Now any pair of ↵Evan Cheng2006-11-011-6/+10
| | | | | | dest / src operands can be tied together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31363 91177308-0d34-0410-b5e6-96231b3b80d8
* restore my previous patch, now that the X86 backend bug has been fixed:Chris Lattner2006-10-121-17/+32
| | | | | | | http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20061009/038518.html git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30906 91177308-0d34-0410-b5e6-96231b3b80d8
* Backing out Chris' last commit. It's breaking llvm-gcc bootstrapping.Evan Cheng2006-10-121-32/+17
| | | | | | | | | | | | | | It's turning: movl -24(%ebp), %esp subl $16, %esp movl -24(%ebp), %ecx into movl -24(%ebp), %esp subl $16, %esp movl %esp, (%esp) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30902 91177308-0d34-0410-b5e6-96231b3b80d8
* If we see a load from a stack slot into a physreg, consider it as providingChris Lattner2006-10-121-17/+32
| | | | | | | the stack slot. This fixes PR943. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30898 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a long-standing wart in the code generator: two-address instruction loweringChris Lattner2006-09-051-55/+44
| | | | | | | | | | | | | | | | actually *removes* one of the operands, instead of just assigning both operands the same register. This make reasoning about instructions unnecessarily complex, because you need to know if you are before or after register allocation to match up operand #'s with the target description file. Changing this also gets rid of a bunch of hacky code in various places. This patch also includes changes to fold loads into cmp/test instructions in the X86 backend, along with a significant simplification to the X86 spill folding code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30108 91177308-0d34-0410-b5e6-96231b3b80d8
* s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|Chris Lattner2006-08-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29911 91177308-0d34-0410-b5e6-96231b3b80d8
* Take advantage of the recent improvements to the liveintervals set (trackingChris Lattner2006-08-241-30/+10
| | | | | | | | | | | | | | | | | | | | instructions which define each value#) to simplify and improve the coallescer. In particular, this patch: 1. Implements iterative coallescing. 2. Reverts an unsafe hack from handlePhysRegDef, superceeding it with a better solution. 3. Implements PR865, "coallescing" away the second copy in code like: A = B ... B = A This also includes changes to symbolically print registers in intervals when possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29862 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a check so that if we have two machine instructions in this formBill Wendling2006-08-211-10/+30
| | | | | | | | | | MOV R0, R1 MOV R1, R0 the second machine instruction is removed. Added a regression test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29792 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate data relocations by using NULL instead of global empty list.Jim Laskey2006-07-211-4/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29250 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce number of exported symbolsAndrew Lenharth2006-07-201-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29220 91177308-0d34-0410-b5e6-96231b3b80d8
* Shave another 27K off libllvmgcc.dylib with visibility hiddenChris Lattner2006-06-281-4/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28973 91177308-0d34-0410-b5e6-96231b3b80d8
* Move some methods out of MachineInstr into MachineOperandChris Lattner2006-05-041-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28102 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a latent bug that my spiller patch last week exposed: we were leavingChris Lattner2006-05-011-0/+4
| | | | | | | | | | instructions in the virtregfolded map that were deleted. Because they were deleted, newly allocated instructions could end up at the same address, magically finding themselves in the map. The solution is to remove entries from the map when we delete the instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28041 91177308-0d34-0410-b5e6-96231b3b80d8
* When promoting a load to a reg-reg copy, where the load was a previousChris Lattner2006-05-011-0/+1
| | | | | | | | instruction folded with spill code, make sure the remove the load from the virt reg folded map. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28040 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove previous patch, which wasn't quite right.Chris Lattner2006-05-011-18/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28039 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove temp. option -spiller-check-liveout, it didn't cause any failure nor ↵Evan Cheng2006-05-011-5/+1
| | | | | | performance regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28029 91177308-0d34-0410-b5e6-96231b3b80d8
* Local spiller kills a store if the folded restore is turned into a copy.Evan Cheng2006-04-301-5/+15
| | | | | | | | | But this is incorrect if the spilled value live range extends beyond the current BB. It is currently controlled by a temporary option -spiller-check-liveout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28024 91177308-0d34-0410-b5e6-96231b3b80d8
* Mapping of physregs can make it so that the designated and input physregs areChris Lattner2006-04-281-0/+13
| | | | | | | the same. In this case, don't emit a noop copy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28008 91177308-0d34-0410-b5e6-96231b3b80d8
* When we have a two-address instruction where the input cannot be clobberedChris Lattner2006-04-281-26/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and is already available, instead of falling back to emitting a load, fall back to emitting a reg-reg copy. This generates significantly better code for some SSE testcases, as SSE has lots of two-address instructions and none of them are read/modify/write. As one example, this change does: pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255 xorps %XMM2, %XMM5 cmpltps %XMM1, %XMM0 - movaps XMMWORD PTR [%ESP + 52], %XMM0 - movapd %XMM6, XMMWORD PTR [%ESP + 52] + movaps %XMM6, %XMM0 cmpltps %XMM6, XMMWORD PTR [%ESP + 68] movapd XMMWORD PTR [%ESP + 52], %XMM6 movaps %XMM6, %XMM0 cmpltps %XMM6, XMMWORD PTR [%ESP + 36] cmpltps %XMM3, %XMM0 - movaps XMMWORD PTR [%ESP + 20], %XMM0 - movapd %XMM7, XMMWORD PTR [%ESP + 20] + movaps %XMM7, %XMM0 cmpltps %XMM7, XMMWORD PTR [%ESP + 4] movapd XMMWORD PTR [%ESP + 20], %XMM7 cmpltps %XMM4, %XMM0 ... which is far better than a store followed by a load! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28001 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug that Evan exposed with some changes he's making, and that wasChris Lattner2006-02-251-9/+23
| | | | | | | | | | exposed with a fastcc problem (breaking pcompress2 on x86 with -enable-x86-fastcc). When reloading a reused reg, make sure to invalidate the reloaded reg, and check to see if there are any other pending uses of the same register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26369 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove debugging printout :)Chris Lattner2006-02-251-5/+6
| | | | | | | Add a minor compile time win, no codegen change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26368 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor some code from being inline to being out in a new class with methods.Chris Lattner2006-02-251-42/+97
| | | | | | | | | This gets rid of two gotos, which is always nice, and also adds some comments. No functionality change, this is just a refactor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26367 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix VC++ warning.Jeff Cohen2006-02-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25957 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle another case exposed on X86.Chris Lattner2006-02-031-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25949 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a nasty problem on two-address machines in the following situation:Chris Lattner2006-02-031-9/+27
| | | | | | | | | | | | | | | | | | | | | | | | | store EAX -> [ss#0] [ss#0] += 1 ... use(EAX) In this case, it is not valid to rewrite this as: store EAX -> [ss#0] EAX += 1 store EAX -> [ss#0] ;;; this would also delete the store above ... use(EAX) ... because EAX is not a dead at that point. Keep track of which registers we are allowed to clobber, and which ones we aren't, and don't clobber the ones we're not supposed to. :) This should resolve the issues on X86 last night. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25948 91177308-0d34-0410-b5e6-96231b3b80d8
* significantly simplify the VirtRegMap code by pulling the SpillSlotsAvailableChris Lattner2006-02-031-70/+98
| | | | | | | | | | and PhysRegsAvailable maps out into a new AvailableSpills struct. No functionality change. This paves the way for a bugfix, coming up next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25947 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix VC++ compilation error caused by using a std::map iterator variable to ↵Jeff Cohen2006-02-031-1/+1
| | | | | | | | | receive a std::multimap iterator value. For some reason, GCC doesn't have a problem with this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25927 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove move copies and dead stuff by not clobbering the result reg of a noop ↵Chris Lattner2006-02-031-12/+21
| | | | | | copy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25926 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify some codeChris Lattner2006-02-031-45/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25924 91177308-0d34-0410-b5e6-96231b3b80d8
* Add code that checks for noop copies, which triggers when either:Chris Lattner2006-02-031-0/+13
| | | | | | | | | | | | | 1. a target doesn't know how to fold load/stores into copies, or 2. the spiller rewrites the input to a copy to the same register as the dest instead of to the reloaded reg. This will be moved/improved in the near future, but allows elimination of some ancient x86 hacks. This eliminates 92 copies from SMG2000 on X86 and 163 copies from 252.eon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25922 91177308-0d34-0410-b5e6-96231b3b80d8
* Physregs may hold multiple stack slot values at the same time. Keep trackChris Lattner2006-02-031-37/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of this, and use it to our advantage (bwahahah). This allows us to eliminate another 60 instructions from smg2000 on PPC (probably significantly more on X86). A common old-new diff looks like this: stw r2, 3304(r1) - lwz r2, 3192(r1) stw r2, 3300(r1) - lwz r2, 3192(r1) stw r2, 3296(r1) - lwz r2, 3192(r1) stw r2, 3200(r1) - lwz r2, 3192(r1) stw r2, 3196(r1) - lwz r2, 3192(r1) + or r2, r2, r2 stw r2, 3188(r1) and - lwz r31, 604(r1) - lwz r13, 604(r1) - lwz r14, 604(r1) - lwz r15, 604(r1) - lwz r16, 604(r1) - lwz r30, 604(r1) + or r31, r30, r30 + or r13, r30, r30 + or r14, r30, r30 + or r15, r30, r30 + or r16, r30, r30 + or r30, r30, r30 Removal of the R = R copies is coming next... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25919 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a deficiency in the spiller that Evan noticed. In particular, considerChris Lattner2006-02-021-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this code: store [stack slot #0], R10 = add R14, [stack slot #0] The spiller didn't know that the store made the value of [stackslot#0] available in R10 *IF* the store came from a copy instruction with the store folded into it. This patch teaches VirtRegMap to look at these stores and recognize the values they make available. In one case Evan provided, this code: divsd %XMM0, %XMM1 movsd %XMM1, QWORD PTR [%ESP + 40] 1) movsd QWORD PTR [%ESP + 48], %XMM1 2) movsd %XMM1, QWORD PTR [%ESP + 48] addsd %XMM1, %XMM0 3) movsd QWORD PTR [%ESP + 48], %XMM1 movsd QWORD PTR [%ESP + 4], %XMM0 turns into: divsd %XMM0, %XMM1 movsd %XMM1, QWORD PTR [%ESP + 40] addsd %XMM1, %XMM0 3) movsd QWORD PTR [%ESP + 48], %XMM1 movsd QWORD PTR [%ESP + 4], %XMM0 In this case, instruction #2 was removed because of the value made available by #1, and inst #1 was later deleted because it is now never used before the stack slot is redefined by #3. This occurs here and there in a lot of code with high spilling, on PPC most of the removed loads/stores are LSU-reject-causing loads, which is nice. On X86, things are much better (because it spills more), where we nuke about 1% of the instructions from SMG2000 and several hundred from eon. More improvements to come... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25917 91177308-0d34-0410-b5e6-96231b3b80d8
* Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far ↵Chris Lattner2006-02-021-2/+3
| | | | | | more logical place. Other methods should also be moved if anyoneis interested. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25913 91177308-0d34-0410-b5e6-96231b3b80d8
* Add explicit #includes of <iostream>Chris Lattner2006-01-221-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25515 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an assertion, update DefInst even though no one uses it (dangling pointersChris Lattner2006-01-041-0/+1
| | | | | | | don't help anyone) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25081 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the LLC regressions on X86 last night. In particular, when undoingChris Lattner2005-10-061-5/+12
| | | | | | | | | | previous copy elisions and we discover we need to reload a register, make sure to use the regclass of the original register for the reload, not the class of the current register. This avoid using 16-bit loads to reload 32-bit values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23645 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in the local spiller, where we could take code like this:Chris Lattner2005-10-051-5/+5
| | | | | | | | | | | | | | | | | | | | | | store r12 -> [ss#2] R3 = load [ss#1] use R3 R3 = load [ss#2] R4 = load [ss#1] and turn it into this code: store R12 -> [ss#2] R3 = load [ss#1] use R3 R3 = R12 R4 = R3 <- oops! The problem was that promoting R3 = load[ss#2] to a copy missed the fact that the instruction invalidated R3 at that point. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23638 91177308-0d34-0410-b5e6-96231b3b80d8
* Change this code ot pass register classes into the stack slot spiller/reloaderChris Lattner2005-09-301-5/+11
| | | | | | | | code. PrologEpilogInserter hasn't been updated yet though, so targets cannot use this info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23536 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the local spiller to turn stack slot loads into register-register copiesChris Lattner2005-09-191-26/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | when possible, avoiding the load (and avoiding the copy if the value is already in the right register). This patch came about when I noticed code like the following being generated: store R17 -> [SS1] ...blah... R4 = load [SS1] This was causing an LSU reject on the G5. This problem was due to the register allocator folding spill code into a reg-reg copy (producing the load), which prevented the spiller from being able to rewrite the load into a copy, despite the fact that the value was already available in a register. In the case above, we now rip out the R4 load and replace it with a R4 = R17 copy. This speeds up several programs on X86 (which spills a lot :) ), e.g. smg2k from 22.39->20.60s, povray from 12.93->12.66s, 168.wupwise from 68.54->53.83s (!), 197.parser from 7.33->6.62s (!), etc. This may have a larger impact in some cases on the G5 (by avoiding LSU rejects), though it probably won't trigger as often (less spilling in general). Targets that implement folding of loads/stores into copies should implement the isLoadFromStackSlot hook to get this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23388 91177308-0d34-0410-b5e6-96231b3b80d8
* Use continue in the use-processing loop to make it clear what the early exitsChris Lattner2005-09-091-115/+123
| | | | | | | | | | are, simplify logic, and cause things to not be nested as deeply. This also uses MRI->areAliases instead of an explicit loop. No functionality change, just code cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23296 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove trailing whitespaceMisha Brukman2005-04-211-11/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21420 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure to notice that explicit physregs are used in the functionChris Lattner2005-04-041-23/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21084 91177308-0d34-0410-b5e6-96231b3b80d8
* Update these register allocators to set the PhysRegUsed info in MachineFunction.Chris Lattner2005-01-231-8/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19791 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve compatibility with accChris Lattner2005-01-141-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19549 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up the MachineBasicBlock.h file, percolating #includes into this file.Chris Lattner2004-10-261-0/+1
| | | | | | | Patch contributed by Morten Ofstad git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17251 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch fixes the nasty bug that caused 175.vpr to fail for X86 last night.Chris Lattner2004-10-151-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The problem occurred when trying to reload this instruction: MOV32mr %reg2326, 8, %reg2297, 4, %reg2295 The value of reg2326 was available in EBX, so it was reused from there, instead of reloading it into EDX. The value of reg2297 was available in EDX, so it was reused from there, instead of reloading it into EDI. The value of reg2295 was not available, so we tried reloading it into EBX, its assigned register. However, we checked and saw that we already reloaded something into EBX, so we chose what reg2326 was assigned to (EDX) and reloaded into that register instead. Unfortunately EDX had already been used by reg2297, so reloading into EDX clobbered the value used by the reg2326 operand, breaking the program. The fix for this is to check that the newly picked register is ok. In this case we now find that EDX is already used and try using EDI, which succeeds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17006 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds and improves debugging output. No functionality changes.Chris Lattner2004-10-151-3/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17005 91177308-0d34-0410-b5e6-96231b3b80d8
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