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* Introducing a new method of tracking register pressure. We can'tAndrew Trick2011-02-044-116/+169
| | | | | | | | | | | | | | | | precisely track pressure on a selection DAG, but we can at least keep it balanced. This design accounts for various interesting aspects of selection DAGS: register and subregister copies, glued nodes, dead nodes, unused registers, etc. Added SUnit::NumRegDefsLeft and ScheduleDAGSDNodes::RegDefIter. Note: I disabled PrescheduleNodesWithMultipleUses when register pressure is enabled, based on no evidence other than I don't think it makes sense to have both enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124853 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugLoc associated with a machine instruction is used to emit location ↵Devang Patel2011-02-041-20/+29
| | | | | | entries. DebugLoc associated with a DBG_VALUE is used to identify lexical scope of the variable. After register allocation, while inserting DBG_VALUE remember original debug location for the first instruction and reuse it, otherwise dwarf writer may be mislead in identifying the variable's scope. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124845 91177308-0d34-0410-b5e6-96231b3b80d8
* Update comments.Evan Cheng2011-02-041-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124843 91177308-0d34-0410-b5e6-96231b3b80d8
* Skip unused values.Jakob Stoklund Olesen2011-02-041-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124842 91177308-0d34-0410-b5e6-96231b3b80d8
* Also compute interference intervals for blocks with no uses.Jakob Stoklund Olesen2011-02-041-3/+1
| | | | | | | | When the live range is live through a block that doesn't use the register, but that has interference, region splitting wants to split at the top and bottom of the basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124839 91177308-0d34-0410-b5e6-96231b3b80d8
* Verify kill flags conservatively.Jakob Stoklund Olesen2011-02-041-18/+5
| | | | | | | | | | Allow a live range to end with a kill flag, but don't allow a kill flag that doesn't end the live range. This makes the machine code verifier more useful during register allocation when kill flag computation is deferred. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124838 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2011-02-031-18/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124827 91177308-0d34-0410-b5e6-96231b3b80d8
* Ensure that the computed interference intervals actually overlap their basic ↵Jakob Stoklund Olesen2011-02-031-3/+12
| | | | | | blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124815 91177308-0d34-0410-b5e6-96231b3b80d8
* Tweak debug output from SlotIndexes.Jakob Stoklund Olesen2011-02-031-1/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124814 91177308-0d34-0410-b5e6-96231b3b80d8
* Add debug output and asserts to the phi-connecting code.Jakob Stoklund Olesen2011-02-031-2/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124813 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix coloring bug when mapping values in the middle of a live-through block.Jakob Stoklund Olesen2011-02-031-7/+7
| | | | | | | | | | If the found value is not live-through the block, we should only add liveness up to the requested slot index. When the value is live-through, the whole block should be colored. Bug found by SSA verification in the machine code verifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124812 91177308-0d34-0410-b5e6-96231b3b80d8
* Return live range end points from SplitEditor::enter*/leave*.Jakob Stoklund Olesen2011-02-033-62/+48
| | | | | | | These end points come from the inserted copies, and can be passed directly to useIntv. This simplifies the coloring code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124799 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence an MSVC warningJakob Stoklund Olesen2011-02-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124798 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply this.Eric Christopher2011-02-034-224/+181
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124779 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert 124765 in an attempt to find the cycle breaking bootstrap.Eric Christopher2011-02-034-181/+224
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124778 91177308-0d34-0410-b5e6-96231b3b80d8
* Defer SplitKit value mapping until all defs are available.Jakob Stoklund Olesen2011-02-034-224/+181
| | | | | | | | | | | | | | | | | | | The greedy register allocator revealed some problems with the value mapping in SplitKit. We would sometimes start mapping values before all defs were known, and that could change a value from a simple 1-1 mapping to a multi-def mapping that requires ssa update. The new approach collects all defs and register assignments first without filling in any live intervals. Only when finish() is called, do we compute liveness and mapped values. At this time we know with certainty which values map to multiple values in a split range. This also has the advantage that we can compute live ranges based on the remaining uses after rematerializing at split points. The current implementation has many opportunities for compile time optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124765 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support to describe template value parameter in debug info.Devang Patel2011-02-022-0/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124755 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support to describe template parameter type in debug info.Devang Patel2011-02-022-0/+32
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124752 91177308-0d34-0410-b5e6-96231b3b80d8
* Given a pair of floating point load and store, if there are no other uses ofEvan Cheng2011-02-021-0/+65
| | | | | | | | | | | | | | | | | | | | the load, then it may be legal to transform the load and store to integer load and store of the same width. This is done if the target specified the transformation as profitable. e.g. On arm, this can transform: vldr.32 s0, [] vstr.32 s0, [] to ldr r12, [] str r12, [] rdar://8944252 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124708 91177308-0d34-0410-b5e6-96231b3b80d8
* Take Bill Wendling's suggestion for structuring a couple of asserts.Matt Beaumont-Gay2011-02-011-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124688 91177308-0d34-0410-b5e6-96231b3b80d8
* Keep track of incoming argument's location while emitting LiveIns.Devang Patel2011-01-314-4/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124611 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.Richard Osborne2011-01-311-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124587 91177308-0d34-0410-b5e6-96231b3b80d8
* Clarify the LSDASection NULL checkAnton Korobeynikov2011-01-301-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124569 91177308-0d34-0410-b5e6-96231b3b80d8
* Respect the -tail-dup-size command line option even when optimizing for size.Jakob Stoklund Olesen2011-01-301-1/+2
| | | | | | | This is similar to the -unroll-threshold option. There should be no change in behavior when -tail-dup-size is not explicit on the llc command line. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124564 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, ↵Benjamin Kramer2011-01-301-0/+23
| | | | | | | | | | | | | | | | | | | c1+c2) when c1 equals the amount of bits that are truncated off. This happens all the time when a smul is promoted to a larger type. On x86-64 we now compile "int test(int x) { return x/10; }" into movslq %edi, %rax imulq $1717986919, %rax, %rax movq %rax, %rcx shrq $63, %rcx sarq $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax" addl %ecx, %eax This fires 96 times in gcc.c on x86-64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124559 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the missing sub identity "A-(A-B) -> B" to DAGCombine.Benjamin Kramer2011-01-291-0/+3
| | | | | | | | | This happens e.g. for code like "X - X%10" where we lower the modulo operation to a series of multiplies and shifts that are then subtracted from X, leading to this missed optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124532 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply r124518 with fix. Watch out for invalidated iterator.Evan Cheng2011-01-291-4/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124526 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r124518. It broke Linux self-host.Evan Cheng2011-01-291-7/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124522 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-commit r124462 with fixes. Tail recursion elim will now dup ret into ↵Evan Cheng2011-01-291-4/+7
| | | | | | unconditional predecessor to enable TCE on demand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124518 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r124462. There are a few big regressions that I need to fix first.Evan Cheng2011-01-281-7/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124478 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix build with stdcxx by using llvm::next. Patch by Joerg Sonnenberger!Nick Lewycky2011-01-281-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124472 91177308-0d34-0410-b5e6-96231b3b80d8
* Print the visibility of declarations.Rafael Espindola2011-01-281-1/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124468 91177308-0d34-0410-b5e6-96231b3b80d8
* - Stop simplifycfg from duplicating "ret" instructions into unconditionalEvan Cheng2011-01-281-4/+7
| | | | | | | | | branches. PR8575, rdar://5134905, rdar://8911460. - Allow codegen tail duplication to dup small return blocks after register allocation is done. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124462 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a temporary workaround for a lencod miscompile. Depends on the fix in ↵Andrew Trick2011-01-271-2/+0
| | | | | | r124442. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124443 91177308-0d34-0410-b5e6-96231b3b80d8
* VirtRegRewriter fix: update kill flags, which are used by the scavenger.Andrew Trick2011-01-271-64/+88
| | | | | | | | | | | | | | | | | | | | | | | | rdar://problem/8893967: JM/lencod miscompile at -arch armv7 -mthumb -O3 Added ResurrectKill to remove kill flags after we decide to reused a physical register. And (hopefully) ensure that we call it in all the right places. Sorry, I'm not checking in a unit test given that it's a miscompile I can't reproduce easily with a toy example. Failures in the rewriter depend on a series of heuristic decisions maked during one of the many upstream phases in codegen. This case would require coercing regalloc to generate a couple of rematerialzations in a way that causes the scavenger to reuse the same register at just the wrong point. The general way to test this is to implement kill flags verification. Then we could have a simple, robust compile-only unit test. That would be worth doing if the whole pass was not about to disappear. At this point we focus verification work on the next generation of regalloc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124442 91177308-0d34-0410-b5e6-96231b3b80d8
* Speculatively revert r124380.Devang Patel2011-01-272-4/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124397 91177308-0d34-0410-b5e6-96231b3b80d8
* While legalizing SDValues do not drop SDDbgValues, trasfer them to new legal ↵Devang Patel2011-01-272-1/+4
| | | | | | | | | nodes. Take 2. This includes fix for dragonegg crash. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124380 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid modifying the OneClassForEachPhysReg map while iterating over it.Bob Wilson2011-01-271-2/+6
| | | | | | | | | Linear scan regalloc is currently assuming that any register aliased with a member of a regclass must also be in at least one regclass. That is not always true. For example, for X86, RIP is in a regclass but IP is not. If you're unlucky, this can cause a crash by invalidating the iterator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124365 91177308-0d34-0410-b5e6-96231b3b80d8
* Try harder to not have unused variables.Matt Beaumont-Gay2011-01-271-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124350 91177308-0d34-0410-b5e6-96231b3b80d8
* Opt-mode -Wunused-variable cleanupMatt Beaumont-Gay2011-01-271-4/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124346 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply 124301Devang Patel2011-01-271-1/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124339 91177308-0d34-0410-b5e6-96231b3b80d8
* Initialize variable to get rid of clang warning.Bill Wendling2011-01-261-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124331 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 124301.Devang Patel2011-01-261-5/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124327 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r124302Devang Patel2011-01-261-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124320 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Add INSERT_SUBVECTOR and support it on x86. This provides aDavid Greene2011-01-262-0/+73
| | | | | | | | | default implementation for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VINSERTF128 if AVX is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124307 91177308-0d34-0410-b5e6-96231b3b80d8
* While legalizing SDValues do not drop SDDbgValues, trasfer them to new legal ↵Devang Patel2011-01-261-0/+3
| | | | | | nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124302 91177308-0d34-0410-b5e6-96231b3b80d8
* Process valid SDDbgValues even if the node does not have any order assigned.Devang Patel2011-01-261-1/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124301 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor.Devang Patel2011-01-261-19/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124300 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Support EXTRACT_SUBVECTOR on x86. This provides a defaultDavid Greene2011-01-262-5/+24
| | | | | | | | | implementation of EXTRACT_SUBVECTOR for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VEXTRACTF128 if AVX is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124292 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename member variables to follow the rest of LLVM.Jakob Stoklund Olesen2011-01-262-295/+295
| | | | | | No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124257 91177308-0d34-0410-b5e6-96231b3b80d8
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