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* Enhance folding of (extract_subvec (insert_subvec V1, V2, IIdx), EIdx)Michael Liao2013-03-251-21/+29
| | | | | | | | | | - Handle the case where the result of 'insert_subvect' is bitcasted before 'extract_subvec'. This removes the redundant insertf128/extractf128 pair on unaligned 256-bit vector load/store on vectors of non 64-bit integer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177945 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable some unsafe-fp-math DAG-combine transformation after legalization.Shuxin Yang2013-03-251-5/+17
| | | | | | | | | | | | | | | For instance, following transformation will be disabled: x + x + x => 3.0f * x; The problem of these transformations is that it introduces a FP constant, which following Instruction-Selection pass cannot handle. Reviewed by Nadav, thanks a lot! rdar://13445387 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177933 91177308-0d34-0410-b5e6-96231b3b80d8
* Couple more sets of tidying.Eric Christopher2013-03-251-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177920 91177308-0d34-0410-b5e6-96231b3b80d8
* Formatting.Eric Christopher2013-03-251-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177898 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach cmake about the new Erlang GC files.Duncan Sands2013-03-252-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177869 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a GC plugin for ErlangYiannis Tsiouris2013-03-252-0/+201
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177867 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the type legality check from the SelectionDAGBuilder when it lowers ↵Owen Anderson2013-03-231-1/+0
| | | | | | | | | | | | @llvm.fmuladd to ISD::FMA nodes. Performing this check unilaterally prevented us from generating FMAs when the incoming IR contained illegal vector types which would eventually be legalized to underlying types that *did* support FMA. For example, an @llvm.fmuladd on an OpenCL float16 should become a sequence of float4 FMAs, not float4 fmul+fadd's. NOTE: Because we still call the target-specific profitability hook, individual targets can reinstate the old behavior, if desired, by simply performing the legality check inside their callback hook. They can also perform more sophisticated legality checks, if, for example, some illegal vector types can be productively implemented as FMAs, but not others. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177820 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comparison of mixed signednessHal Finkel2013-03-231-1/+1
| | | | | | | | | | | 177774 broke the lld-x86_64-darwin11 builder; error: error: comparison of integers of different signs: 'int' and 'size_type' (aka 'unsigned long') for (SI = 0; SI < Scavenged.size(); ++SI) ~~ ^ ~~~~~~~~~~~~~~~~ Fix this by making SI also unsigned. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177780 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow the register scavenger to spill multiple registersHal Finkel2013-03-222-21/+40
| | | | | | | | | | | | | | | | | | This patch lets the register scavenger make use of multiple spill slots in order to guarantee that it will be able to provide multiple registers simultaneously. To support this, the RS's API has changed slightly: setScavengingFrameIndex / getScavengingFrameIndex have been replaced by addScavengingFrameIndex / isScavengingFrameIndex / getScavengingFrameIndices. In forthcoming commits, the PowerPC backend will use this capability in order to implement the spilling of condition registers, and some special-purpose registers, without relying on r0 being reserved. In some cases, spilling these registers requires two GPRs: one for addressing and one to hold the value being transferred. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove ScavengedRC from RegisterScavengingHal Finkel2013-03-221-3/+0
| | | | | | | ScavengedRC was a dead private variable (set, but not otherwise used). No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177708 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix missing std::. Not sure how this compiles for anyone else.Matt Arsenault2013-03-211-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177620 91177308-0d34-0410-b5e6-96231b3b80d8
* Make variable name more explicit and eliminate redundant lookup in ↵Justin Holewinski2013-03-201-4/+4
| | | | | | SDNodeOrdering git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177600 91177308-0d34-0410-b5e6-96231b3b80d8
* When computing the demanded bits of Load SDNodes, make sure that we are ↵Nadav Rotem2013-03-201-12/+16
| | | | | | | | | | looking at the loaded-value operand and not the ptr result (in case of pre-inc loads). rdar://13348420 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177596 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "pre-RA-sched: fix TargetOpcode usage"Christian Konig2013-03-201-18/+12
| | | | | | | | | | | | This reverts commit 06091513c283c863296f01cc7c2e86b56bb50d02. The code is obviously wrong, but the trivial fix causes inefficient code generation on X86. Somebody with more knowledge of the code needs to take a look here. Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177529 91177308-0d34-0410-b5e6-96231b3b80d8
* Move SDNode order propagation to SDNodeOrdering, which also fixes a missedJustin Holewinski2013-03-204-23/+15
| | | | | | | | case of order propagation during isel. Thanks Owen for the suggestion! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177525 91177308-0d34-0410-b5e6-96231b3b80d8
* pre-RA-sched: fix TargetOpcode usageChristian Konig2013-03-201-12/+18
| | | | | | | | TargetOpcodes need to be treaded as Machine- and not ISD-Opcodes. Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177518 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate DAG node ordering during type legalization and instruction selectionJustin Holewinski2013-03-203-2/+43
| | | | | | | | A node's ordering is only propagated during legalization if (a) the new node does not have an ordering (is not a CSE'd node), or (b) the new node has an ordering that is higher than the node being legalized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177465 91177308-0d34-0410-b5e6-96231b3b80d8
* Move #include of BitVector from .h to .cpp file.Jakub Staszak2013-03-181-0/+1
| | | | | | | Also remove unneeded #include and forward declaration. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177357 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some constantness.Jakub Staszak2013-03-181-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177356 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix integer comparison in DIEInteger::BestForm.Hans Wennborg2013-03-181-3/+4
| | | | | | | The always-true "(int)Int == (signed)Int" comparison was found while experimenting with a potential new Clang warning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177290 91177308-0d34-0410-b5e6-96231b3b80d8
* Windows TLS: Section name prefix to ensure correct orderAnton Korobeynikov2013-03-181-2/+5
| | | | | | | | | | | | | The linker sorts the .tls$<xyz> sections by name, and we need to make sure any extra sections we produce (e.g. for weak globals) always end up between .tls$AAA and .tls$ZZZ, even if the name starts with e.g. an underscore. Patch by David Nadlinger! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177256 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the default latency for implicit defs.Andrew Trick2013-03-161-1/+4
| | | | | | | | | | | | | | | | Implicit defs are not currently positional and not modeled by the per-operand machine model. Unfortunately, we treat defs that are part of the architectural instruction description, like flags, the same as other implicit defs. Really, they should have a fixed MachineInstr layout and probably shouldn't be "implicit" at all. For now, we'll change the default latency to be the max operand latency. That will give flag setting operands full latency for x86 folded loads. Other kinds of "fake" implicit defs don't occur prior to regalloc anyway, and we would like them to go away postRegAlloc as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177227 91177308-0d34-0410-b5e6-96231b3b80d8
* Move estimateStackSize from ARM into MachineFrameInfoHal Finkel2013-03-141-0/+48
| | | | | | | | | | This is a generic function (derived from PEI); moving it into MachineFrameInfo eliminates a current redundancy between the ARM and AArch64 backends, and will allow it to be used by the PowerPC target code. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177111 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide the register scavenger to processFunctionBeforeFrameFinalizedHal Finkel2013-03-141-1/+1
| | | | | | | | | | | | | Add the current PEI register scavenger as a parameter to the processFunctionBeforeFrameFinalized callback. This change is necessary in order to allow the PowerPC target code to set the register scavenger frame index after the save-area offset adjustments performed by processFunctionBeforeFrameFinalized. Only after these adjustments have been made is it possible to estimate the size of the stack frame. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177108 91177308-0d34-0410-b5e6-96231b3b80d8
* Reset some of the target options which affect code generation.Bill Wendling2013-03-131-0/+1
| | | | | | | | | This doesn't reset all of the target options within the TargetOptions object. This is because some of those are ABI-specific and must be determined if it's okay to change those on the fly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176986 91177308-0d34-0410-b5e6-96231b3b80d8
* No functionality change. Use unreachable in getCUOffset.Manman Ren2013-03-131-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176963 91177308-0d34-0410-b5e6-96231b3b80d8
* No functionality change. Use unreachable in getCompileUnit.Manman Ren2013-03-131-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176962 91177308-0d34-0410-b5e6-96231b3b80d8
* Check register classes also when changing them.Jakob Stoklund Olesen2013-03-131-0/+1
| | | | | | We have the same assertion in createVirtualRegister. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176959 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: use DW_FORM_ref_addr instead of DW_FORM_ref4 if the referenced DIEManman Ren2013-03-126-4/+54
| | | | | | | | | | | | | | | | | belongs to a different compile unit. DW_FORM_ref_addr should be used for cross compile-unit reference. When compiling a large application, we got a dwarfdump verification error where abstract_origin points to nowhere. This error can't be reproduced on any testing case in MultiSource. We may have other cases where we use DW_FORM_ref4 unconditionally. rdar://problem/13370501 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176882 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid generating ISD::SELECT for vector operands to SIGN_EXTENDRichard Relph2013-03-121-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176881 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove support for versioned debug info.David Blaikie2013-03-113-143/+24
| | | | | | | | | | | | | | | | | | | | | | | | Versioned debug info support has been a burden to maintain & also compromised current debug info verification by causing test cases testing old debug info to remain rather than being updated to the latest. It also makes it hard to add or change the metadata schema by requiring various backwards-compatibility in the DI* hierarchy. So it's being removed in preparation for new changes to the schema to tidy up old/unnecessary fields and add new fields needed for new debug info (well, new to LLVM at least). The more surprising part of this is the changes to DI*::Verify - this became necessary due to the changes to AsmWriter. AsmWriter was relying on the version test to decide which bits of metadata were actually debug info when printing the comment annotations. Without the version information the tag numbers were too common & it would print debug info on random metadata that happened to start with an integer that matched a tag number. Instead this change makes the Verify functions more precise (just adding "number of operands" checks - not type checking those operands yet) & relies on that to decide which metadata is debug info metadata. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176838 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a crasher newly introduced in r176659/r176649, where fast-isel tries toNick Lewycky2013-03-111-0/+2
| | | | | | | lower an expect intrinsic that is a constant expression. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176830 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup #includes.Jakub Staszak2013-03-101-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176787 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove wrong and unnecessary assertion.Jakob Stoklund Olesen2013-03-081-1/+0
| | | | | | | PHIs are allowed to have multiple operand pairs per predecessor, and this code works just fine when it happens. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176734 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable statistics on Release builds and move tests that depend on -stats.Jan Wen Voung2013-03-082-18/+14
| | | | | | | | | | | | | | | | | Summary: Statistics are still available in Release+Asserts (any +Asserts builds), and stats can also be turned on with LLVM_ENABLE_STATS. Move some of the FastISel stats that were moved under DEBUG() back out of DEBUG(), since stats are disabled across the board now. Many tests depend on grepping "-stats" output. Move those into a orig_dir/Stats/. so that they can be marked as unsupported when building without statistics. Differential Revision: http://llvm-reviews.chandlerc.com/D486 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176733 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite the physreg part of findLastUseBefore().Jakob Stoklund Olesen2013-03-081-24/+36
| | | | | | | | | To find the last use of a register unit, start from the bottom and scan upwards until a user is found. <rdar://problem/13353090> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176706 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove default from fully covered switch.Benjamin Kramer2013-03-081-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176703 91177308-0d34-0410-b5e6-96231b3b80d8
* LegalizeDAG: Respect the result of TLI.getBooleanContents() when expanding SETCCTom Stellard2013-03-081-1/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176695 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombiner: Use correct value type for checking legality of BR_CC v3Tom Stellard2013-03-081-1/+2
| | | | | | | | | | | | | LegalizeDAG.cpp uses the value of the comparison operands when checking the legality of BR_CC, so DAGCombiner should do the same. v2: - Expand more BR_CC value types for NVPTX v3: - Expand correct BR_CC value types for Hexagon, Mips, and XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176694 91177308-0d34-0410-b5e6-96231b3b80d8
* Add -verify-misched option.Andrew Trick2013-03-081-0/+9
| | | | | | | | | | This verifies live intervals both before and after scheduling. It's useful for anyone hacking on live interval update. Note that we don't yet pass verification all the time. We don't yet handle updating nonallocatable live intervals perfectly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176685 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r176154 in favor of a better approach.Bill Wendling2013-03-082-9/+11
| | | | | | | | | | | | | | | | | | | | Code generation makes some basic assumptions about the IR it's been given. In particular, if there is only one 'invoke' in the function, then that invoke won't be going away. However, with the advent of the `llvm.donothing' intrinsic, those invokes may go away. If all of them go away, the landing pad no longer has any users. This confuses the back-end, which asserts. This happens with SjLj exceptions, because that's the model that modifies the IR based on there being invokes, etc. in the function. Remove any invokes of `llvm.donothing' during SjLj EH preparation. This will give us a CFG that the back-end won't be confused about. If all of the invokes in a function are removed, then the SjLj EH prepare pass won't insert the bogus code the relies upon the invokes being there. <rdar://problem/13228754&13316637> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176677 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a getPassName() method.Jakob Stoklund Olesen2013-03-071-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176669 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename isEarlierInSameTrace to isUsefulDominator.Jakob Stoklund Olesen2013-03-071-2/+2
| | | | | | | | | | | | | | In very rare cases caused by irreducible control flow, the dominating block can have the same trace head without actually being part of the trace. As long as such a dominator still has valid instruction depths, it is OK to use it for computing instruction depths. Rename the function to avoid lying, and add a check that instruction depths are computed for the dominator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176668 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] Seriously, add support for the expect intrinsic.Chad Rosier2013-03-071-3/+3
| | | | | | rdar://13370942 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176659 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] Add support for the expect intrinsic.Chad Rosier2013-03-071-0/+5
| | | | | | rdar://13370942 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176649 91177308-0d34-0410-b5e6-96231b3b80d8
* ArrayRefize some code. No functionality change.Benjamin Kramer2013-03-072-5/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176648 91177308-0d34-0410-b5e6-96231b3b80d8
* pre-RA-sched debug-only fixAndrew Trick2013-03-071-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176638 91177308-0d34-0410-b5e6-96231b3b80d8
* pre-RA-sched assertion fix. This bug was exposed by r176037.Andrew Trick2013-03-071-3/+0
| | | | | | | | | | | | | rdar:13370002 [pre-RA-sched] assertion: released too many times I tracked this down to an earlier hack that is no longer applicable and interfered with normal scheduler logic. With the changes in r176037, it was causing an instruction to be scheduled multiple times. I have an external test case that I tried hard to reduce and failed. I can't even reproduce with llc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176636 91177308-0d34-0410-b5e6-96231b3b80d8
* No need to go through int64 and APInt when generating a new constant.Nadav Rotem2013-03-071-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176615 91177308-0d34-0410-b5e6-96231b3b80d8
* SDAG: Handle scalarizing an extend of a <1 x iN> vector.Jim Grosbach2013-03-072-0/+21
| | | | | | | | | Just scalarize the element and rebuild a vector of the result type from that. rdar://13281568 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176614 91177308-0d34-0410-b5e6-96231b3b80d8
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