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* Continue after removing the current MI.Evan Cheng2008-09-191-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56372 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor X86SelectConstAddr, folding it into X86SelectAddress. ThisDan Gohman2008-09-191-21/+15
| | | | | | | | results in better code for globals. Also, unbreak the local CSE for GlobalValue stub loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56371 91177308-0d34-0410-b5e6-96231b3b80d8
* Make earlyclobber stuff work when virtual regsDale Johannesen2008-09-191-8/+26
| | | | | | | | have previously been assigned conflicting physreg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56364 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-materalized definition instructions may be dead. Whack them.Evan Cheng2008-09-192-7/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56352 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysisDale Johannesen2008-09-193-73/+79
| | | | | | | | | and redo as linked list walk. Logic moved into RA. Per review feedback. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56326 91177308-0d34-0410-b5e6-96231b3b80d8
* Somehow RegAllocLinearScan is keeping two pointers to MachineRegisterInfo.Evan Cheng2008-09-181-8/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56314 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't consider instructions with implicit physical registerDan Gohman2008-09-181-1/+2
| | | | | | | defs to be necessarily live. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56310 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new "fast" scheduler. This is currently basically just aDan Gohman2008-09-181-0/+654
| | | | | | | | | | | | | | | | | copy of the BURRList scheduler, but with several parts ripped out, such as backtracking, online topological sort maintenance (needed by backtracking), the priority queue, and Sethi-Ullman number computation and maintenance (needed by the priority queue). As a result of all this, it generates somewhat lower quality code, but that's its tradeoff for running about 30% faster than list-burr in -fast mode in many cases. This is somewhat experimental. Moving forward, major pieces of this can be refactored with pieces in common with ScheduleDAGRRList.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56307 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a bit to mark operands of asm's that conflictDale Johannesen2008-09-177-26/+140
| | | | | | | | | | | with an earlyclobber operand elsewhere. Propagate this bit and the earlyclobber bit through SDISel. Change linear-scan RA not to allocate regs in a way that conflicts with an earlyclobber. See also comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56290 91177308-0d34-0410-b5e6-96231b3b80d8
* Unallocatable registers do not have live intervals.Evan Cheng2008-09-171-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56287 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't worry about clobbering physical register defs that aren't used.Dan Gohman2008-09-171-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56281 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new MachineInstr-level DCE pass. It is very simple, and is intended toDan Gohman2008-09-171-0/+99
| | | | | | | be used with fast-isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56268 91177308-0d34-0410-b5e6-96231b3b80d8
* When converting a CopyFromReg to a copy instruction, use the register class ↵Evan Cheng2008-09-161-5/+24
| | | | | | of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56258 91177308-0d34-0410-b5e6-96231b3b80d8
* Change SelectionDAG::getConstantPool to always set the alignment of theDan Gohman2008-09-162-7/+20
| | | | | | | | | | | | | | | | | | | | | ConstantPoolSDNode, using the target's preferred alignment for the constant type. In LegalizeDAG, when performing loads from the constant pool, the ConstantPoolSDNode's alignment is used in the calls to getLoad and getExtLoad. This change prevents SelectionDAG::getLoad/getExtLoad from incorrectly choosing the ABI alignment for constant pool loads when Alignment == 0. The incorrect alignment is only a performance issue when ABI alignment does not equal preferred alignment (i.e., on x86 it was generating MOVUPS instead of MOVAPS for v4f32 constant loads when the default ABI alignment for 128bit vectors is forced to 1 byte.) Patch by Paul Redmond! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56253 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverting r56249. On further investigation, this functionality isn't needed.Bill Wendling2008-09-166-59/+45
| | | | | | | Apologies for the thrashing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56251 91177308-0d34-0410-b5e6-96231b3b80d8
* Include the alignment value when displaying ConstantPoolSDNodes.Dan Gohman2008-09-161-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56250 91177308-0d34-0410-b5e6-96231b3b80d8
* - Change "ExternalSymbolSDNode" to "SymbolSDNode".Bill Wendling2008-09-166-45/+59
| | | | | | | | | | | - Add linkage to SymbolSDNode (default to external). - Change ISD::ExternalSymbol to ISD::Symbol. - Change ISD::TargetExternalSymbol to ISD::TargetSymbol These changes pave the way to allowing SymbolSDNodes with non-external linkage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56249 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix these comments to reflect current reality. Surprisingly,Dan Gohman2008-09-161-1/+2
| | | | | | | | MachineConstantPool::getConstantPoolIndex actually expects a log2-encoded alignment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56248 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't take the time to CheckDAGForTailCallsAndFixThem when tail callsDan Gohman2008-09-162-4/+10
| | | | | | | | are not enabled. Instead just omit the tail call flag when calls are created. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56235 91177308-0d34-0410-b5e6-96231b3b80d8
* Live intervals for live-in registers should begin at the beginning of a ↵Owen Anderson2008-09-151-7/+11
| | | | | | | | | | basic block, not at the first instruction. Also, their valno's should have an unknown def. This has no effect currently, but was causing issues when StrongPHIElimination was enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56231 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-enable SelectionDAG CSE for calls. It matters in the case ofDan Gohman2008-09-151-6/+20
| | | | | | | libcalls, as in this testcase on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56226 91177308-0d34-0410-b5e6-96231b3b80d8
* Correctly update kill infos after extending a live range and merge 2 val#'s; ↵Evan Cheng2008-09-151-3/+8
| | | | | | fix 56165 - do not mark val# copy field if the copy does not define the val#. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56199 91177308-0d34-0410-b5e6-96231b3b80d8
* adjust last patch per review feedbackDale Johannesen2008-09-141-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56194 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove isImm(), isReg(), and friends, in favor of Dan Gohman2008-09-139-29/+30
| | | | | | | | | | isImmediate(), isRegister(), and friends, to avoid confusion about having two different names with the same meaning. I'm not attached to the longer names, and would be ok with changing to the shorter names if others prefer it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56189 91177308-0d34-0410-b5e6-96231b3b80d8
* Define CallSDNode, an SDNode subclass for use with ISD::CALL.Dan Gohman2008-09-135-59/+73
| | | | | | | | | | | | | | Currently it just holds the calling convention and flags for isVarArgs and isTailCall. And it has several utility methods, which eliminate magic 5+2*i and similar index computations in several places. CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle nodes that are not CSE'd gracefully. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56183 91177308-0d34-0410-b5e6-96231b3b80d8
* On some targets, non-move instructions can become move instructions because ↵Evan Cheng2008-09-121-14/+28
| | | | | | | | | | | | | of coalescing. e.g. vr2 = OR vr0, vr1 => vr2 = OR vr1, vr1 // after coalescing vr0 with vr1 Update the value# of the destination register with the copy instruction if that happens. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56165 91177308-0d34-0410-b5e6-96231b3b80d8
* Change ConstantSDNode and ConstantFPSDNode to use ConstantInt* andDan Gohman2008-09-125-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | | ConstantFP* instead of APInt and APFloat directly. This reduces the amount of time to create ConstantSDNode and ConstantFPSDNode nodes when ConstantInt* and ConstantFP* respectively are already available, as is the case in SelectionDAGBuild.cpp. Also, it reduces the amount of time to legalize constants into constant pools, and the amount of time to add ConstantFP operands to MachineInstrs, due to eliminating ConstantInt::get and ConstantFP::get calls. It increases the amount of work needed to create new constants in cases where the client doesn't already have a ConstantInt* or ConstantFP*, such as legalize expanding 64-bit integer constants to 32-bit constants. And it adds a layer of indirection for the accessor methods. But these appear to be outweight by the benefits in most cases. It will also make it easier to make ConstantSDNode and ConstantFPNode more consistent with ConstantInt and ConstantFP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56162 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass "earlyclobber" bit through to machineDale Johannesen2008-09-123-5/+20
| | | | | | | | | representation; coalescer and RA need to know about it. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56161 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman2008-09-1211-128/+143
| | | | | | | | with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
* The sequence for ppcf128 compares was not IEEEDale Johannesen2008-09-121-4/+6
| | | | | | | | safe in the presence of NaNs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56136 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR2748. Avoid coalescing physical register with virtual register which ↵Evan Cheng2008-09-112-0/+70
| | | | | | | | | | | | would create illegal extract_subreg. e.g. vr1024 = extract_subreg vr1025, 1 ... vr1024 = mov8rr AH If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56118 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR2783 - coalescer bug. Missing a TargetRegisterInfo::isVirtualRegister ↵Evan Cheng2008-09-111-1/+2
| | | | | | check. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56112 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a 80 column violation.Evan Cheng2008-09-111-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56097 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate subreg index when promoting a load to a copy.Evan Cheng2008-09-111-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56085 91177308-0d34-0410-b5e6-96231b3b80d8
* FastISel support for i1 PHI nodes.Dan Gohman2008-09-101-2/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56069 91177308-0d34-0410-b5e6-96231b3b80d8
* FastISel support for i1 constants.Dan Gohman2008-09-101-2/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56068 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in the coalescer where it didn't check if a live interval existed ↵Owen Anderson2008-09-101-1/+1
| | | | | | | | | before trying to manipulate it. This was exposed by fast isel's handling of shifts on X86-64. With this, FreeBench/pcompress2 passes on X86-64 in fast isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56067 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86FastISel support for static allocas, and refencesDan Gohman2008-09-102-14/+23
| | | | | | | | to static allocas. As part of this change, refactor the address mode code for laods and stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56066 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR2664 - spiller GetRegForReload wasn't respecting sub-register indices ↵Evan Cheng2008-09-101-2/+4
| | | | | | on machine operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56065 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a break statement that I accidentally deleted whenDan Gohman2008-09-101-0/+1
| | | | | | | | I shuffled the fast-isel command-line options around. This fixes a bunch of fast-isel failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56057 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary bit-wise AND from the limited precision work.Bill Wendling2008-09-101-6/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56049 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix 80 col violation.Daniel Dunbar2008-09-101-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56048 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo.Evan Cheng2008-09-101-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56037 91177308-0d34-0410-b5e6-96231b3b80d8
* Check that both operands are f32 before attempting to lower.Bill Wendling2008-09-101-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56036 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement "visitPow". This is mainly used to see if we have a pow() call of thisBill Wendling2008-09-102-4/+146
| | | | | | | | | | | | form: powf(10.0f, x); If this is the case, and also we want limited precision floating-point calculations, then lower to do the limited-precision stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56035 91177308-0d34-0410-b5e6-96231b3b80d8
* A few more places where FPOW is being ignored.Evan Cheng2008-09-091-7/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56032 91177308-0d34-0410-b5e6-96231b3b80d8
* Change -fast-isel-no-abort to -fast-isel-abort, which now defaultsDan Gohman2008-09-091-7/+12
| | | | | | | | | to being off by default. Also, add assertion checks to check that the various fast-isel-related command-line options are only used when -fast-isel itself is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56029 91177308-0d34-0410-b5e6-96231b3b80d8
* Legalizer was missing code that expand fpow to a libcall.Evan Cheng2008-09-091-10/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56028 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding 6-, 12-, and 18-bit limited-precision floating-point support for exp2Bill Wendling2008-09-091-26/+111
| | | | | | | function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56025 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the uglier parts of deciding not to emit aDale Johannesen2008-09-091-15/+4
| | | | | | | | | | | UsedDirective for some symbols in llvm.used into Darwin-specific code. I've decided LessPrivateGlobal is potentially a useful abstraction and left it in the target-independent area, with improved comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56024 91177308-0d34-0410-b5e6-96231b3b80d8
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