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* Preserve <def,undef> flags in CoalesceExtSubRegs.Jakob Stoklund Olesen2012-01-241-3/+7
* Revert r148686 (and r148694, a fix to it) due to a serious layeringChandler Carruth2012-01-241-20/+5
* Remove extraneous ';'s.Bill Wendling2012-01-231-1/+1
* copyImplicitOps is redundant here - the loop above already copies these ops.Lang Hames2012-01-231-1/+0
* Fix PR11829. PostRA LICM was too aggressive.Jakob Stoklund Olesen2012-01-231-4/+4
* Simplify debug output.Jakob Stoklund Olesen2012-01-231-10/+2
* An option to selectively enable parts of ARM EHABI support.Evgeniy Stepanov2012-01-231-5/+20
* Add an option to disable buggy copy propagation passAnton Korobeynikov2012-01-221-1/+3
* Fix an obvious typo.Evan Cheng2012-01-211-1/+1
* Handle register masks in LiveVariables.Jakob Stoklund Olesen2012-01-211-0/+30
* Delete an unused member variable.Jakob Stoklund Olesen2012-01-202-2/+0
* Support register masks in MachineLICM.Jakob Stoklund Olesen2012-01-201-23/+36
* Handle register masks in DeadMachineInstructionElim.Jakob Stoklund Olesen2012-01-201-0/+7
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-2015-46/+12
* Extend Attributes to 64 bitsKostya Serebryany2012-01-201-2/+2
* When lowering the 'resume' instruction, look to see if we can eliminate theBill Wendling2012-01-201-2/+32
* More bundle related API additions.Evan Cheng2012-01-191-1/+52
* Rewriter should definitly rewrite instructions inside bundles.Evan Cheng2012-01-191-2/+2
* Enhance finalizeBundle to return end of bundle iterator because it makes sense.Evan Cheng2012-01-191-3/+6
* - Slight change to finalizeBundle() interface. LastMI is not exclusive (pointingEvan Cheng2012-01-191-3/+18
* Rename Finalizebundle to finalizeBundle to conform to coding guideline.Evan Cheng2012-01-191-2/+2
* Add a RegisterMaskSDNode class.Jakob Stoklund Olesen2012-01-184-2/+22
* Fixed macro condition.Lang Hames2012-01-181-1/+1
* Fix a bug in the type-legalization of vector integers. When we bitcast one ve...Nadav Rotem2012-01-181-2/+4
* Fix ISD::REG_SEQUENCE to accept physical registers and change TwoAddressInstr...Pete Cooper2012-01-182-16/+24
* Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.Nadav Rotem2012-01-171-4/+35
* Teach DAG combiner to turn a BUILD_VECTOR of UNDEFs into an UNDEF of vector t...Craig Topper2012-01-171-4/+8
* misched: Inital interface and implementation for ScheduleTopDownLive and Shuf...Andrew Trick2012-01-171-17/+130
* Renamed MachineScheduler to ScheduleTopDownLive.Andrew Trick2012-01-174-51/+63
* Moving options declarations around.Andrew Trick2012-01-172-2/+7
* Add 148175 back. I am unable to reproduce any non determinism in a dragoneggRafael Espindola2012-01-171-2/+4
* Changed flag operand of ISD::FP_ROUND to TargetConstant as it should not get ...Pete Cooper2012-01-171-2/+3
* Fix typo in comment.Lang Hames2012-01-171-1/+1
* Removing unused default switch cases in switches over enums that already acco...David Blaikie2012-01-161-1/+1
* AggressiveAntiDepBreaker needs to skip debug values because a debug value doe...Hal Finkel2012-01-161-0/+3
* Extract method for detecting constant unallocatable physregs.Jakob Stoklund Olesen2012-01-164-41/+21
* Give better scavenger errors by invoking the verifier.Jakob Stoklund Olesen2012-01-161-1/+6
* Add a new kind of MachineOperand: MO_RegisterMask.Jakob Stoklund Olesen2012-01-161-0/+5
* Refactor variables unused under non-assert builds (& remove two entirely unus...David Blaikie2012-01-161-2/+0
* Changed intrinsic ID operand to a target constant as its not used in any arit...Pete Cooper2012-01-161-1/+1
* [AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.Nadav Rotem2012-01-151-5/+22
* Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through Code...Benjamin Kramer2012-01-151-7/+5
* DAGCombiner: Deduplicate code.Benjamin Kramer2012-01-151-24/+14
* Truncate of undef is just undef of smaller size.Craig Topper2012-01-151-5/+6
* Speculatively revert commit 148175 (rafael), to see if this fixesDuncan Sands2012-01-141-4/+2
* Only emit the Leh_func_endN symbol when needed.Rafael Espindola2012-01-141-2/+4
* misched: Initial code for building an MI level scheduling DAGAndrew Trick2012-01-144-21/+113
* Move physreg dependency generation into aptly named addPhysRegDeps.Andrew Trick2012-01-142-155/+182
* misched: Added ScheduleDAGInstrs::IsPostRAAndrew Trick2012-01-144-11/+17
* misched: Invoke the DAG builder on each sequence of schedulable instructions.Andrew Trick2012-01-141-6/+31