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* Refactor the code to grab the low and high parts of a valueDan Gohman2009-04-254-126/+38
| | | | | | | using EXTRACT_ELEMENT into a utility function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70056 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a top-level comment about DAGCombiner's role in the compiler.Dan Gohman2009-04-251-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70052 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not share a single unknown val# for all the live ranges merged into a ↵Evan Cheng2009-04-251-19/+13
| | | | | | physical sub-register live interval. When coalescer is merging in clobbered virtaul register live interval into a physical register live interval, give each virtual register val# a separate val# in the physical register live interval. Otherwise, the coalescer would have lost track of the definitions information it needs to make correct coalescing decisions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70026 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR 4057, a crash doing float->char const folding.Dale Johannesen2009-04-241-3/+4
| | | | | | | | | | This particular one is undefined behavior (although this isn't related to the crash), so it will no longer do it at compile time, which seems better. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69990 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 69952. Causes testsuite failures on linux x86-64.Rafael Espindola2009-04-245-353/+447
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69967 91177308-0d34-0410-b5e6-96231b3b80d8
* PR2957Nate Begeman2009-04-245-447/+353
| | | | | | | | | | | | | | | ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes as the shuffle mask. A value of -1 represents UNDEF. In addition to eliminating the creation of illegal BUILD_VECTORS just to represent shuffle masks, we are better about canonicalizing the shuffle mask, resulting in substantially better code for some classes of shuffles. A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69952 91177308-0d34-0410-b5e6-96231b3b80d8
* Instead of requiring TLI.LowerCallTo to return an ISD::BUILD_PAIR,Dan Gohman2009-04-241-60/+118
| | | | | | | | | use ISD::EXTRACT_ELEMENT. SelectionDAG has a special fast-path for the cast of an EXTRACT_ELEMENT with a BUILD_PAIR operand, for the common case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69948 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor out a bit of code that appears in several places into aDan Gohman2009-04-233-14/+16
| | | | | | | utility function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69937 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle Void types in ComputeValueVTs. This doesn't currently occur,Dan Gohman2009-04-231-0/+3
| | | | | | | | but this change makes the code more general and easier to adapt for new purposes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69935 91177308-0d34-0410-b5e6-96231b3b80d8
* Update comments.Evan Cheng2009-04-231-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69919 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an obvious type.Evan Cheng2009-04-231-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69918 91177308-0d34-0410-b5e6-96231b3b80d8
* It has finally happened. Spiller is now using live interval info.Evan Cheng2009-04-215-40/+68
| | | | | | | This fixes a very subtle bug. vr defined by an implicit_def is allowed overlap with any register since it doesn't actually modify anything. However, if it's used as a two-address use, its live range can be extended and it can be spilled. The spiller must take care not to emit a reload for the vn number that's defined by the implicit_def. This is both a correctness and performance issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69743 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Visual Studio 2008 build failure.Devang Patel2009-04-211-3/+3
| | | | | | | | Patch by Marius Wachtler git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69637 91177308-0d34-0410-b5e6-96231b3b80d8
* Make X86's copyRegToReg able to handle copies to and from subclasses.Dan Gohman2009-04-201-25/+0
| | | | | | | | This makes the extra copyRegToReg calls in ScheduleDAGSDNodesEmit.cpp unnecessary. Derived from a patch by Jakob Stoklund Olesen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69635 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify this code. getConstant knows how to makeDan Gohman2009-04-201-10/+3
| | | | | | | broadcasted vector constants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69634 91177308-0d34-0410-b5e6-96231b3b80d8
* Move duplicated AddLiveIn function from X86 and ARM backends to be a methodBob Wilson2009-04-201-0/+10
| | | | | | | | in the MachineFunction class, renaming it to addLiveIn for consistency with the same method in MachineBasicBlock. Thanks for Anton for suggesting this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69615 91177308-0d34-0410-b5e6-96231b3b80d8
* Revise my previous change 68996 as suggested by Duncan.Bob Wilson2009-04-203-9/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69607 91177308-0d34-0410-b5e6-96231b3b80d8
* - Remove an arbitrary spill weight tweak that should not have been there.Evan Cheng2009-04-201-5/+26
| | | | | | | - Find more reloads from SS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69606 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a linearscan register allocation optimization. When the register ↵Evan Cheng2009-04-202-67/+189
| | | | | | | | | | | | | | | | | | | | | | | | | | | allocator spill an interval with multiple uses in the same basic block, it creates a different virtual register for each of the reloads. e.g. %reg1498<def> = MOV32rm %reg1024, 1, %reg0, 12, %reg0, Mem:LD(4,4) [sunkaddr39 + 0] %reg1506<def> = MOV32rm %reg1024, 1, %reg0, 8, %reg0, Mem:LD(4,4) [sunkaddr42 + 0] %reg1486<def> = MOV32rr %reg1506 %reg1486<def> = XOR32rr %reg1486, %reg1498, %EFLAGS<imp-def,dead> %reg1510<def> = MOV32rm %reg1024, 1, %reg0, 4, %reg0, Mem:LD(4,4) [sunkaddr45 + 0] => %reg1498<def> = MOV32rm %reg2036, 1, %reg0, 12, %reg0, Mem:LD(4,4) [sunkaddr39 + 0] %reg1506<def> = MOV32rm %reg2037, 1, %reg0, 8, %reg0, Mem:LD(4,4) [sunkaddr42 + 0] %reg1486<def> = MOV32rr %reg1506 %reg1486<def> = XOR32rr %reg1486, %reg1498, %EFLAGS<imp-def,dead> %reg1510<def> = MOV32rm %reg2038, 1, %reg0, 4, %reg0, Mem:LD(4,4) [sunkaddr45 + 0] From linearscan's point of view, each of reg2036, 2037, and 2038 are separate registers, each is "killed" after a single use. The reloaded register is available and it's often clobbered right away. e.g. In thise case reg1498 is allocated EAX while reg2036 is allocated RAX. This means we end up with multiple reloads from the same stack slot in the same basic block. Now linearscan recognize there are other reloads from same SS in the same BB. So it'll "downgrade" RAX (and its aliases) after reg2036 is allocated until the next reload (reg2037) is done. This greatly increase the likihood reloads from SS are reused. This speeds up sha1 from OpenSSL by 5.8%. It is also an across the board win for SPEC2000 and 2006. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69585 91177308-0d34-0410-b5e6-96231b3b80d8
* Now that BUILD_VECTOR operands are allowed to beDuncan Sands2009-04-191-9/+6
| | | | | | | | | bigger than the vector element type, turn checking of the operand type back on again, appropriately adjusted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69516 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR3898, which manifests as failures on are an Xcore,Chris Lattner2009-04-181-1/+1
| | | | | | | patch by Jakob Stoklund Olesen! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69472 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't try to make BUILD_VECTOR operands have the sameDuncan Sands2009-04-186-63/+35
| | | | | | | | | | | | | | | | | | type as the vector element type: allow them to be of a wider integer type than the element type all the way through the system, and not just as far as LegalizeDAG. This should be safe because it used to be this way (the old type legalizer would produce such nodes), so backends should be able to handle it. In fact only targets which have legal vector types with an illegal promoted element type will ever see this (eg: <4 x i16> on ppc). This fixes a regression with the new type legalizer (vec_splat.ll). Also, treat SCALAR_TO_VECTOR the same as BUILD_VECTOR. After all, it is just a special case of BUILD_VECTOR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69467 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new LiveInterval::overlaps(). It checks if the live interval overlaps ↵Evan Cheng2009-04-181-0/+16
| | | | | | a range specified by [Start, End). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69434 91177308-0d34-0410-b5e6-96231b3b80d8
* Inline asm's were still introducing bogus dependencies;Dale Johannesen2009-04-181-1/+7
| | | | | | | | my earlier patch to this code only fixed half of it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69408 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach spiller to unfold instructions which modref spill slot when a scratchEvan Cheng2009-04-172-11/+227
| | | | | | | | | | | | | | | | | | | | | register is available and when it's profitable. e.g. xorq %r12<kill>, %r13 addq %rax, -184(%rbp) addq %r13, -184(%rbp) ==> xorq %r12<kill>, %r13 movq -184(%rbp), %r12 addq %rax, %r12 addq %r13, %r12 movq %r12, -184(%rbp) Two more instructions, but fewer memory accesses. It can also open up opportunities for more optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69341 91177308-0d34-0410-b5e6-96231b3b80d8
* In the list-burr's pseudo two-addr dependency heuristics, don'tDan Gohman2009-04-161-0/+10
| | | | | | | | | | add dependencies on nodes with exactly one successor which is a COPY_TO_REGCLASS node. In the case that the copy is coalesced away, the dependence should be on the user of the copy, rather than the copy itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69309 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle SUBREG_TO_REG instructions with the same heuristicsDan Gohman2009-04-161-5/+7
| | | | | | | as INSERT_SUBREG instructions in the list-burr scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69308 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not treat beginning of inlined scope as beginning of normal function ↵Devang Patel2009-04-162-2/+20
| | | | | | | | | | | | | | | | | | | | | | | scope if the location info is missing. Insetad of doing ... if (inlined_subroutine && known_location) DW_TAG_inline_subroutine else DW_TAG_subprogram do if (inlined_subroutine) { if (known_location) DW_TAG_inline_subroutine } else { DW_TAG_subprogram } git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69300 91177308-0d34-0410-b5e6-96231b3b80d8
* Record line number at the beginning of a func.start.Devang Patel2009-04-162-2/+2
| | | | | | | This line was accidently lost yesterday. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69286 91177308-0d34-0410-b5e6-96231b3b80d8
* In -fast mode do what FastISel does.Devang Patel2009-04-162-30/+71
| | | | | | | This code could use some refactoring help! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69254 91177308-0d34-0410-b5e6-96231b3b80d8
* If FastISel is run and it has known DebugLoc then use it.Devang Patel2009-04-162-3/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69253 91177308-0d34-0410-b5e6-96231b3b80d8
* If location where the function was inlined is not know then do not emit ↵Devang Patel2009-04-161-5/+11
| | | | | | debug info describing inlinied region. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69252 91177308-0d34-0410-b5e6-96231b3b80d8
* s/RootDbgScope/FunctionDbgScope/gDevang Patel2009-04-151-13/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69216 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DISubprogram is not null check.Devang Patel2009-04-151-2/+4
| | | | | | | This fixes test/CodeGen//2009-01-21-invalid-debug-info.m test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69210 91177308-0d34-0410-b5e6-96231b3b80d8
* Generalize one of the SelectionDAG::ReplaceAllUsesWith overloadsDan Gohman2009-04-152-9/+10
| | | | | | | | | to support replacing a node with another that has a superset of the result types. Use this instead of calling ReplaceAllUsesOfValueWith for each value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69209 91177308-0d34-0410-b5e6-96231b3b80d8
* Check isInlinedSubroutine() before creating DW_TAG_inlined_subroutine.Devang Patel2009-04-151-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69202 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix MachineInstr::getNumExplicitOperands to countDan Gohman2009-04-151-2/+2
| | | | | | | variadic operands correctly. Patch by Jakob Stoklund Olesen! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69190 91177308-0d34-0410-b5e6-96231b3b80d8
* Move MachineRegisterInfo::setRegClass out of line.Dan Gohman2009-04-151-0/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69126 91177308-0d34-0410-b5e6-96231b3b80d8
* Move MachineJumpTableInfo::ReplaceMBBInJumpTables out of line.Dan Gohman2009-04-151-0/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69125 91177308-0d34-0410-b5e6-96231b3b80d8
* Give RemoveRegOperandFromRegInfo a comment and move theDan Gohman2009-04-151-0/+15
| | | | | | | code out of line. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69124 91177308-0d34-0410-b5e6-96231b3b80d8
* Construct and emit DW_TAG_inlined_subroutine DIEs for inlined subroutine ↵Devang Patel2009-04-153-91/+217
| | | | | | scopes (only in FastISel mode). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69116 91177308-0d34-0410-b5e6-96231b3b80d8
* When the result of an EXTRACT_SUBREG, INSERT_SUBREG, or SUBREG_TO_REGDan Gohman2009-04-141-20/+19
| | | | | | | | | | | | | operator is used by a CopyToReg to export the value to a different block, don't reuse the CopyToReg's register for the subreg operation result if the register isn't precisely the right class for the subreg operation. Also, rename the h-registers.ll test, now that there are more than one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69087 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not force asm's to be chained if they don't touchDale Johannesen2009-04-141-0/+3
| | | | | | | | | memory and aren't volatile. This was interfering with good scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69008 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR3934 part 2. findOnlyInterestingUse() was not setting IsCopy and ↵Evan Cheng2009-04-141-9/+13
| | | | | | IsDstPhys which are returned by value and used by callee. This happened to work on the earlier test cases because of a logic error in the caller side. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69006 91177308-0d34-0410-b5e6-96231b3b80d8
* Make these errors more noticable in build logs.Daniel Dunbar2009-04-131-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68998 91177308-0d34-0410-b5e6-96231b3b80d8
* Change SelectionDAG type legalization to allow BUILD_VECTOR operands to beBob Wilson2009-04-135-31/+78
| | | | | | | | | | | | | | | | | | | | | | | | | promoted to legal types without changing the type of the vector. This is following a suggestion from Duncan (http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-February/019923.html). The transformation that used to be done during type legalization is now postponed to DAG legalization. This allows the BUILD_VECTORs to be optimized and potentially handled specially by target-specific code. It turns out that this is also consistent with an optimization done by the DAG combiner: a BUILD_VECTOR and INSERT_VECTOR_ELT may be combined by replacing one of the BUILD_VECTOR operands with the newly inserted element; but INSERT_VECTOR_ELT allows its scalar operand to be larger than the element type, with any extra high bits being implicitly truncated. The result is a BUILD_VECTOR where one of the operands has a type larger the the vector element type. Any code that operates on BUILD_VECTORs may now need to be aware of the potential type discrepancy between the vector element type and the BUILD_VECTOR operands. This patch updates all of the places that I could find to handle that case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68996 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman2009-04-132-14/+13
| | | | | | | | it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor some code in SelectionDAGLegalize::ExpandBUILD_VECTOR.Bob Wilson2009-04-131-24/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68981 91177308-0d34-0410-b5e6-96231b3b80d8
* PR3934: Fix a bogus two-address pass assertion.Evan Cheng2009-04-131-8/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68979 91177308-0d34-0410-b5e6-96231b3b80d8
* Right now, Debugging information to encode scopes (DW_TAG_lexical_block) ↵Devang Patel2009-04-133-21/+24
| | | | | | | | | relies on DBG_LABEL. Unfortunately this intefers with the quality of optimized code. This patch updates dwarf writer to encode scoping information in DWARF only in FastISel mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68973 91177308-0d34-0410-b5e6-96231b3b80d8
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