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* Give targets a chance to expand even standard pseudos.Jakob Stoklund Olesen2011-10-101-4/+12
| | | | | | | | | | | Allow targets to expand COPY and other standard pseudo-instructions before they are expanded with copyPhysReg(). This allows the target to examine the COPY instruction for extra operands indicating it can be widened to a preferable super-register copy. See the ARM -widen-vmovs option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141578 91177308-0d34-0410-b5e6-96231b3b80d8
* If loop header is also loop exiting block then it may not be safe to hoist ↵Devang Patel2011-10-101-5/+4
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141576 91177308-0d34-0410-b5e6-96231b3b80d8
* Add dominance check for the instruction being hoisted.Devang Patel2011-10-101-0/+30
| | | | | | | | For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141569 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the code that lowers the arguments and spills any values which are aliveBill Wendling2011-10-081-2/+125
| | | | | | | | | across unwind edges. This is for the back-end which expects such things. The code is from the original SjLj EH pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141463 91177308-0d34-0410-b5e6-96231b3b80d8
* Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented toBill Wendling2011-10-071-2/+8
| | | | | | | do. This will be useful later on with the new SJLJ stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141416 91177308-0d34-0410-b5e6-96231b3b80d8
* PostRA scheduler fix. Clear stale loop dependencies.Andrew Trick2011-10-072-1/+3
| | | | | | | Fixes <rdar://problem/10235725> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141357 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2011-10-072-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141356 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the old atomic instrinsics. autoupgrade functionality is included ↵Eli Friedman2011-10-062-67/+0
| | | | | | with this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141333 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify the mapping from landing pad to call sites to accept more than one callBill Wendling2011-10-053-3/+6
| | | | | | | site. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141226 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an ivar that maps a landing pad's EH symbol to the call sites that may jumpBill Wendling2011-10-051-0/+8
| | | | | | | | to the landing pad. This will be used by the back-end to generate the jump tables for dispatching the arriving longjmp in sjlj eh. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141224 91177308-0d34-0410-b5e6-96231b3b80d8
* Small refactoring. Cache the FunctionInfo->MBB into a local variable.Bill Wendling2011-10-051-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141221 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix sub-register operand verification.Jakob Stoklund Olesen2011-10-051-12/+25
| | | | | | | | | PhysReg operands are not allowed to have sub-register indices at all. For virtual registers with sub-reg indices, check that all registers in the register class support the sub-reg index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141220 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment to reflect the new EH stuff.Bill Wendling2011-10-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141218 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused DstSubIdx argument.Jakob Stoklund Olesen2011-10-051-23/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141214 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify EXTRACT_SUBREG emission.Jakob Stoklund Olesen2011-10-052-27/+52
| | | | | | | | | | | | EXTRACT_SUBREG is emitted as %dst = COPY %src:sub, so there is no need to constrain the %dst register class. RegisterCoalescer will apply the necessary constraints if it decides to eliminate the COPY. The %src register class does need to be constrained to something with the right sub-registers, though. This is currently done manually with COPY_TO_REGCLASS nodes. They can possibly be removed after this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141207 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify INSERT_SUBREG emission.Jakob Stoklund Olesen2011-10-051-27/+19
| | | | | | | | | | | | | | The register class created by INSERT_SUBREG and SUBREG_TO_REG must be legal and support the SubIdx sub-registers. The new getSubClassWithSubReg() hook can compute that. This may create INSERT_SUBREG instructions defining a larger register class than the sub-register being inserted. That is OK, RegisterCoalescer will constrain the register class as needed when it eliminates the INSERT_SUBREG instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141198 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a FIXME.Jakob Stoklund Olesen2011-10-051-0/+4
| | | | | | | | TwoAddressInstructionPass should annotate instructions with <undef> flags when it lower REG_SEQUENCE instructions. LiveIntervals should not be in the business of modifying code (except for kill flags, perhaps). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141187 91177308-0d34-0410-b5e6-96231b3b80d8
* Also add <imp-use,kill> flags for redefined super-registers.Jakob Stoklund Olesen2011-10-051-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | For example: %vreg10:dsub_0<def,undef> = COPY %vreg1 %vreg10:dsub_1<def> = COPY %vreg2 is rewritten as: %D2<def> = COPY %D0, %Q1<imp-def> %D3<def> = COPY %D1, %Q1<imp-use,kill>, %Q1<imp-def> The first COPY doesn't care about the previous value of %Q1, so it doesn't read that register. The second COPY is a partial redefinition of %Q1, so it implicitly kills and redefines that register. This makes it possible to recognize instructions that can harmlessly clobber the full super-register. The write and don't read the super-register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141139 91177308-0d34-0410-b5e6-96231b3b80d8
* Also add <def,undef> flags when coalescing sub-registers.Jakob Stoklund Olesen2011-10-051-0/+8
| | | | | | | | RegisterCoalescer can create sub-register defs when it is joining a register with a sub-register. Add <undef> flags to these new sub-register defs where appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141138 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the MC to output code/data region marker labels in MachO and ELF ↵Owen Anderson2011-10-041-1/+12
| | | | | | modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141135 91177308-0d34-0410-b5e6-96231b3b80d8
* Create a mapping between the landing pad basic block and the call site index ↵Bill Wendling2011-10-042-0/+5
| | | | | | for later use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141125 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow <undef> flags on def operands as well as uses.Jakob Stoklund Olesen2011-10-041-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The <undef> flag says that a MachineOperand doesn't read its register, or doesn't depend on the previous value of its register. A full register def never depends on the previous register value. A partial register def may depend on the previous value if it is intended to update part of a register. For example: %vreg10:dsub_0<def,undef> = COPY %vreg1 %vreg10:dsub_1<def> = COPY %vreg2 The first copy instruction defines the full %vreg10 register with the bits not covered by dsub_0 defined as <undef>. It is not considered a read of %vreg10. The second copy modifies part of %vreg10 while preserving the rest. It has an implicit read of %vreg10. This patch adds a MachineOperand::readsReg() method to determine if an operand reads its register. Previously, this was modelled by adding a full-register <imp-def> operand to the instruction. This approach makes it possible to determine directly from a MachineOperand if it reads its register. No scanning of MI operands is required. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141124 91177308-0d34-0410-b5e6-96231b3b80d8
* Generic cleanup.Bill Wendling2011-10-041-23/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141050 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't carry over the dispatchsetup hack from the old system.Bill Wendling2011-10-031-7/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141040 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the grabbing of the jump buffer into the caller function, eliminating ↵Bill Wendling2011-10-031-31/+33
| | | | | | the need for returning a std::pair. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141026 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace.Eric Christopher2011-10-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141005 91177308-0d34-0410-b5e6-96231b3b80d8
* Typo.Eric Christopher2011-10-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141004 91177308-0d34-0410-b5e6-96231b3b80d8
* Moved type construction out of the loop and added an assert on the legality ↵Nadav Rotem2011-10-011-10/+10
| | | | | | of the type. Formatted lines to the 80 char limit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140952 91177308-0d34-0410-b5e6-96231b3b80d8
* When inferring the pointer alignment, if the global doesn't have an initializerBill Wendling2011-09-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | and the alignment is 0 (i.e., it's defined globally in one file and declared in another file) it could get an alignment which is larger than the ABI allows for that type, resulting in aligned moves being used for unaligned loads. For instance, in file A.c: struct S s; In file B.c: struct { // something long }; extern S s; void foo() { struct S p = s; // ... } this copy is a 'memcpy' which is turned into a series of 'movaps' instructions on X86. But this is wrong, because 'struct S' has alignment of 4, not 16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140902 91177308-0d34-0410-b5e6-96231b3b80d8
* Promote comment to doxycomment. Adjust whitespace. No functionality change.Nick Lewycky2011-09-301-4/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140899 91177308-0d34-0410-b5e6-96231b3b80d8
* Move getCommonSubClass() into TRI.Jakob Stoklund Olesen2011-09-304-9/+10
| | | | | | It will soon need the context. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140896 91177308-0d34-0410-b5e6-96231b3b80d8
* Comment grammar fixes.Torok Edwin2011-09-301-5/+6
| | | | | | thanks to Duncan. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140850 91177308-0d34-0410-b5e6-96231b3b80d8
* Instead of crashing when MCAsmInfo is NULL, add an assert.Torok Edwin2011-09-301-0/+5
| | | | | | | This helps with porting code from 2.9 to 3.0 as TargetSelect.h changed location, and if you include the old one by accident you will trigger this assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140848 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up uses of switch instructions so they are not dependent on the ↵Eli Friedman2011-09-291-2/+2
| | | | | | operand ordering. Patch by Stepan Dyatkovskiy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140803 91177308-0d34-0410-b5e6-96231b3b80d8
* Place this bracket according to the LLVM style.Duncan Sands2011-09-291-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140784 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove NumImplicitOps which is now unused.Jakob Stoklund Olesen2011-09-291-18/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140767 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the local we already set up.Eric Christopher2011-09-291-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140745 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite MachineInstr::addOperand() to avoid NumImplicitOps.Jakob Stoklund Olesen2011-09-291-81/+53
| | | | | | | | | | | | | | | | | | | | | | | The function needs to scan the implicit operands anyway, so no performance is won by caching the number of implicit operands added to an instruction. This also fixes a bug when adding operands after an implicit operand has been added manually. The NumImplicitOps count wasn't kept up to date. MachineInstr::addOperand() will now consistently place all explicit operands before all the implicit operands, regardless of the order they are added. It is possible to change an MI opcode and add additional explicit operands. They will be inserted before any existing implicit operands. The only exception is inline asm instructions where operands are never reordered. This is because of a hack that marks explicit clobber regs on inline asm as <implicit-def> to please the fast register allocator. This hack can go away when InstrEmitter and FastIsel can add exact <dead> flags to physreg defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140744 91177308-0d34-0410-b5e6-96231b3b80d8
* Have the SjLjEHPrepare pass do some more heavy lifting.Bill Wendling2011-09-281-34/+55
| | | | | | | | | Upon further review, most of the EH code should remain written at the IR level. The part which breaks SSA form is the dispatch table, so that part will be moved to the back-end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140730 91177308-0d34-0410-b5e6-96231b3b80d8
* A typeid of zero means a cleanup, not a catch. This case occursDuncan Sands2011-09-281-2/+4
| | | | | | | when there is both a catch and a cleanup. Correct the comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140686 91177308-0d34-0410-b5e6-96231b3b80d8
* Strip off pointer casts when looking at the eh.sjlj.functioncontext's argument.Bill Wendling2011-09-281-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140678 91177308-0d34-0410-b5e6-96231b3b80d8
* Bitcast the alloca to an i8* to match the intrinsic's signature.Bill Wendling2011-09-281-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140677 91177308-0d34-0410-b5e6-96231b3b80d8
* Create and use an llvm.eh.sjlj.functioncontext intrinsic.Bill Wendling2011-09-282-0/+14
| | | | | | | | | This intrinsic is used to pass the index of the function context to the back-end for further processing. The back-end is in charge of filling in the rest of the entries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140676 91177308-0d34-0410-b5e6-96231b3b80d8
* In the new EH model, setup the function context and the call site info.Bill Wendling2011-09-281-1/+181
| | | | | | | | | | | | | The DWARF exception pass uses the call site information, which is set up here. A pre-RA pass is too late for it to use this information. So create and setup the function context here, and then insert the call site values here (and map the call sites for the DWARF EH pass). This is simpler than the original pass, and doesn't make the CFG lose its SSA-ness. It's a win-win-win-win-lose-win-win situation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140675 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't conditionalize execution of the SjLj EH prepare pass.Bill Wendling2011-09-281-5/+1
| | | | | | | | We may need an SjLj EH preparation pass for some call site information, at least in the short term. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140674 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename class and clean up source.Jakob Stoklund Olesen2011-09-281-25/+28
| | | | | | No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140664 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix.Jakob Stoklund Olesen2011-09-282-0/+521
| | | | | | I'll clean up the source in the next commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140663 91177308-0d34-0410-b5e6-96231b3b80d8
* This is the start of the new SjLj EH preparation pass, which will replace theBill Wendling2011-09-271-1/+5
| | | | | | | | | | | | | | | | | | | | current IR-level pass. The old SjLj EH pass has some problems, especially with the new EH model. Most significantly, it violates some of the new restrictions the new model has. For instance, the 'dispatch' table wants to jump to the landing pad, but we cannot allow that because only an invoke's unwind edge can jump to a landing pad. This requires us to mangle the code something awful. In addition, we need to keep the now dead landingpad instructions around instead of CSE'ing them because the DWARF emitter uses that information (they are dead because no control flow edge will execute them - the control flow edge from an invoke's unwind is superceded by the edge coming from the dispatch). Basically, this pass belongs not at the IR level where SSA is king, but at the code-gen level, where we have more flexibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140646 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove an invalid assert that is really just asserting when the scheduler emitsCameron Zwarich2011-09-271-1/+0
| | | | | | a suboptimal schedule. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140643 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().Jim Grosbach2011-09-271-2/+2
| | | | | | Naming conventions consistency. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140636 91177308-0d34-0410-b5e6-96231b3b80d8
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