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path: root/lib/Target/ARM/ARMBaseInstrInfo.cpp
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* Add sizes non-floating point versions for the eh sjlj intrinsic expansions.Jim Grosbach2010-04-281-1/+2
* Add ARM specific emitFrameIndexDebugValue.Evan Cheng2010-04-261-0/+10
* Educate GetInstrSizeInBytes implementations thatDale Johannesen2010-04-071-0/+1
* use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-4/+4
* Teach AnalyzeBranch, RemoveBranch and the branchDale Johannesen2010-04-021-1/+14
* Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.Bob Wilson2010-03-231-2/+6
* Rename some instructions to match the corresponding NEON opcode.Bob Wilson2010-03-231-2/+2
* Change VST1 instructions for loading Q register values to operate on pairsBob Wilson2010-03-231-1/+1
* Change VLD1 instructions for loading Q register values to operate on pairsBob Wilson2010-03-231-1/+1
* Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")Bob Wilson2010-03-201-4/+3
* Refactor Reg-Reg copy emission routine for ARM. This makes cross-regclass cop...Anton Korobeynikov2010-03-181-29/+39
* Revert 98683. It is breaking something in the disassembler.Bob Wilson2010-03-161-3/+4
* Remove redundant writeback flag from ARM address mode 6. Also remove theBob Wilson2010-03-161-4/+3
* - Change MachineInstr::isIdenticalTo to take a new option that determines whe...Evan Cheng2010-03-031-4/+3
* Handle tGPR register class in a few more places. This fixes some llvm-gccBob Wilson2010-02-161-0/+10
* Fix pr6111: Avoid using the LR register for the target address of an indirectBob Wilson2010-02-161-0/+7
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-4/+4
* tighten up eh.setjmp sequence a bit.Jim Grosbach2010-02-081-2/+2
* Adjust setjmp instruction sequence to not need 32-bit alignment paddingJim Grosbach2010-01-271-1/+1
* prep work to support a future where getJumpTableInfo will returnChris Lattner2010-01-251-0/+1
* For aligned load/store instructions, it's only required to know whether aJim Grosbach2010-01-191-2/+2
* Add Target hook to duplicate machine instructions.Jakob Stoklund Olesen2010-01-061-21/+46
* Remove dead variable.Bill Wendling2009-12-281-2/+0
* remove out of date FIXME.Jim Grosbach2009-12-031-1/+0
* fix a build problem with VC++, PR5664, patch by Alp Toker!Chris Lattner2009-12-031-2/+4
* Thumb1 exception handling setjmpJim Grosbach2009-12-011-0/+2
* Remove isProfitableToDuplicateIndirectBranch target hook. It is profitableBob Wilson2009-11-301-6/+0
* Refactor target hook for tail duplication as requested by Chris.Bob Wilson2009-11-241-6/+2
* Enable predication of NEON instructions in Thumb2 mode.Evan Cheng2009-11-241-5/+1
* Add predicate operand to NEON instructions. Fix lots (but not all) 80 col vio...Evan Cheng2009-11-211-12/+35
* Also CSE non-pic load from constant pools.Evan Cheng2009-11-201-1/+4
* Add a target hook to allow changing the tail duplication limit based on theBob Wilson2009-11-181-0/+10
* Detect need for autoalignment of the stack earlier to catch spills moreJim Grosbach2009-11-151-0/+1
* set the def of the VLD1q64 properlyJim Grosbach2009-11-151-2/+1
* - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.Evan Cheng2009-11-141-1/+8
* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-091-21/+21
* Use aligned load/store instructions for spilling Q registers when we know the...Jim Grosbach2009-11-081-6/+23
* Refactor code.Evan Cheng2009-11-081-0/+54
* 80-column cleanup of file header commentsJim Grosbach2009-11-071-1/+1
* Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRp...Evan Cheng2009-11-071-0/+33
* Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So i...Evan Cheng2009-11-031-1/+1
* Trim unnecessary include.Evan Cheng2009-11-031-1/+0
* Clean up copyRegToReg.Evan Cheng2009-11-031-27/+13
* Turn neon reg-reg moves fixup code into separate pass. This should reduce the...Anton Korobeynikov2009-11-031-33/+2
* Unbreak ARMBaseRegisterInfo::copyRegToReg.Evan Cheng2009-11-021-18/+19
* Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls,...Anton Korobeynikov2009-11-021-8/+46
* Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate theBob Wilson2009-10-281-1/+2
* Don't forget subreg indices when folding load / store.Evan Cheng2009-10-251-10/+30
* 80 col violation.Evan Cheng2009-10-241-1/+2
* -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixedEvan Cheng2009-10-181-8/+2
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